This is a tool can generate a DDR3 script easily for i.Mx6DQSDL and only need input several parameters based on using DDR datasheet and system architecture.
Following docs(English or Chinese version) are also can be referred as a hand on guide.
Freescale i.MX6 DRAM Port Application Guide-DDR3
Please find i.Mx6DQP DDR3 Script Aid through below link.
MX6DQP DDR3 Script Aid
Please find i.Mx6DQSDL LPDDR2 Script Aid through below link.
i.Mx6DQSDL LPDDR2 Script Aid
Please find i.Mx6SL LPDDR2 Script Aid through below link.
i.MX6SL LPDDR2 Script Aid
Please find i.MX6SX DDR3 Script Aid through below link.
i.MX6SX DDR3 Script Aid
Please find I.MX53 DDR3 Script Aid through below link.
I.MX53 DDR3 Script Aid
i.MX6 DDR Stress Test Tool
Any questions are welcome!
0.11 updateadd note for duty cycle consideration.
Thanks for the tool. A couple of questions:
1) The fine tuning calibration procedure in the "Calibration" worksheet talks about testing Read Delay for PHY0 (Set #1). It gives the example of a byte 2 failure:
Expect value 0x55555555, but read back 0x55515555
This seems clear that it's a byte 2 failure for PHY0.
Then it describes another failure:
Expect value 0xFFFFFFFFFFFFFFFF, but read back 0xFFFFFFEFFFFFFFFF.
It says that that this would be a byte 0 error and that lower 32 bits belong to other (PHY1). I'm not sure I understand why the error isn't a Byte 0 error on PHY1 (set 2).
I seems like in the first example, the lower 32 bits refer to PHY0, but in the second example the upper 32 bits refer to PHY0. Can you clarify this?
2) How many loops of the stresstest are needed for each iteration in fine tuning max and min. Can we skip row hopping when fine tuning?
1. It's a bug in DDR_Stress_Tester_V0.042, PHY0 and PHY1 are swapped in 64bit test output. We had fixed it and please wait next release.
2. Generally we think it is ok when stress test can pass more than 3 loops under min or max corner. Of cause more loops and mutil-condition(different temperature,complex electronmagnitic field) will get more precise result.
Sorry I can't understand what's "Row hopping". Please follow the fine tuning process no skip.
Thanks for the info Lin. In the version of the DDR stress test I have it asks:
"Do you want to run the 'row hop' test? (y/n)"
That's what I was referring to when I said "row hopping".
There is no this function in latest version "DDR_Stress_Tester_V0.042".
You may use an old version.
CS0_END should be set to DDR_CS_size/32M + 0x7 (ddr space begins at 0x10000000)
For example, if the CS size is 1G, the CS0_END should be set to 1G /32M + 0x7 = 0x27.
Is that compatible for i.MX6 sololite?. If not, do you have a DDR3 script for i.MX6SL that I can use?
This Aid isn't for i.Mx6SL DDR3.
But you can use it as a reference(I believe most settings are same).
Please ask FSL supporter for i.Mx6SL DDR3 script.
I'm new in this community. May I know where I can reach the FSL supporter for i.MX6SL DDR3 script? Is it here or different forums?.
I mean finding FSL FAE or other contact window for help!
FSL will provide design service for customer.
Thanks for the info. I got the script.
Simple question: Where can I download the DDR Stress tester kit? When searching www.freescale.com, I find only an 2011 version for iMX5
Please ask help from local FAE.
It seems this excel can't work with Microsoft Office Excel 2003 (11.8169.8172) SP3. When modify bus width from 64 to 16 in worksheet "Register Configuration". Column 167 in worksheet "RealView .inc" will show "#NAME?".
Seems you mentioned excel is not "i.Mx6DQSDL DDR3 Script Aid".
Please try the excel in this page.
Result of using excel in this page as below.
Please use MS-Excel 2007, I use 2007 creating the file.
Hi Lin, this is how it is being used in u-boot as well, but I was just looking at the imx6q reference manual which says :
in section 44.12.16 MMDC Core Address Space Partition Register (MMDCx_MDASP)
CS0_END. Defines the absolute last address associated with CS0 with increments of 256Mb.
001_1111 8Gb (1GB)
011_1111 16Gb (2GB) - default
111_1111 32Gb (4GB)
So is this referring to something else or the reference manual is not accurate.
Yes, you are right.
This description had been modified in upcoming releasing.
Please find below as a reference before new RM version ready.
For 6DQ and 6SDL:
CS0_END CS0_END. Defines the absolute last address associated with CS0 with increments of 256Mb.
In DDR3 and 1-channel LPDDR2 mode:
MMDCx _MDASP[CS0_END] should be set to DDR_CS_SIZE/32MB + 0x7 (DDR base address begins at 0x10000000)
In 2-channel LPDDR2 mode:
MMDC0_MDASP[CS0_END] should be set to DDR_CS_SIZE/32M + 0x3f (channel 0 base address begins at 0x80000000)
MMDC1_MDASP[CS0_END] should be set to DDR_CS_SIZE/32M + 0x7 (channel 1 base address begins at 0x10000000);
In 2-channel LPDDR2 with 4k-interleave mode:
MMDC0_MDASP[CS0_END] should be set to DDR_CS_SIZE/32M + 0x43;
MMDC1_MDASP[CS0_END] should be set to DDR_CS_SIZE/32M + 0x3;
Great thanks ...
Hi Lin Wang,
I tested a i.MX6Q custom board with this stress test tool.
But, the log seems that test was failure as below.
For your information, "Address of failure" value and "Data was" value will change each time I run the stress test.
Then, I want to confirm meaning of this failure.
Is this failure caused by DDR signal integrity?
Or caused by other defect?
Please make sure DDR chip info had been configured properly in page Register Configuration of "Aid”.
Second WL,DQS and write&read calibration are also should be done before running stress test.
Please check above first.
I used this aid tool and got a calibration data.
Then, I want to confirm what file should I apply the calibration data.
My understanding is as below.
Is this correct?
For LTIB BSP:
For Yocto BSP:
Especially, I want to confirm about Yocto because I will use it.
Sorry I am not a SW guy.
Please rise a new ticket for asking your question.
I believe a SW guy can answer your question easily.
OK, I will create a new ticket, thank you.
Hi Ling Wang,
I want to confirm what is "System ODT Setting (ohm)".
Is this ODT of i.MX6 which is set by MMDCx_MPODTCTRL register (chapter 44.12.38 in IMX6DQRM Rev.1)?
Or is this ODT of DDR3 set by MMDCx_MDSCR register (chapter 44.12.9)?
I think it should be 0 ohm if it is i.MX6 ODT, but the initial value was 60 ohm when I downloaded the script aid.
60 ohm is same as DDR3 ODT (MT41K128M16) setting, so I'm confused.
According to correspondence between this value and the setting in RealView.inc sheet, I guess user should input DDR3 ODT to "System ODT Setting (ohm)".
Is this right?
"System ODT Setting (ohm)" will impact both i.MX6 side and DDR3 side.
You can find some hints through changing ODT value and compare the changes in register side.
I checked the RealView.int sheet again, and I confirmed both DDR3 and i.MX6 ODT setting is changed by "System ODT Setting (ohm)", thank you.
By the way, according to <u-boot dir>/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg, I understood MCIMX6Q-SDP ODT setting by L3.10.17_1.0.0-ga BSP as below.
DDR3 ODT = 60 ohm (RTT,NOM & RTT(WR))
i.MX6 ODT = 120 ohm (RTT,NOM)
In this case, what value should I set to "System ODT Setting (ohm)"?
The configuration in our BSP is trade off between stability and power consumption.
The tool don't support fine tune function, user should study and modify the register directly if they have such requirement.
OK, I understood.
Thank you for your cooperation.
For the SI Configuration, I don't know how to set the value of DESE and ODT. How to select the impedance values for different case? Look forward the reply, thank you!
Suggest to use simulation tool to investigate it.
Our customer want to use DDR3-1066 chip with i.MX6Dual Lite.
In this case, the DDR chip works as DDR3-800 because i.MX6DL max DDR frequency is 400MHz, doen't it?
Then, could you give me advice which value (DDR3-1066 spec or DDR3-800 spec) in DDR datasheet should they input to the following items of the script aid?
Memory ppart number:
tRCD=tRP=CL (ns) :
tRC Min (ns) :
tRAS Min (ns) :
I believe you can get the answer from below doc.
Thank you for your quick response, and sorry I overlooked the document.
I understood our customer should input DDR3-1066 spec in the case.
Thank you for your good support.
A couple of us have been working on dynamic IMX6 MMDC configuration in the mainline uboot for SPL support and have noticed some discrepancies between your spreadsheet and the reference manuals that perhaps you can explain:
1. The IMX6 TRM states that bit16 of the MAPSR register is reserved and defaults to 0 on reset, yet the spreadsheet/script sets this to 1. Is this an error in the script or is there something missing from the TRM that we should know about?
2. The spreadsheet/script sets MDPDC bit7 SLOW_PD=0 indicating fast precharge PD mode, yet the MR0 value written to the DRAM sets bit12=0 indicating slow precharge PD. The TRM states in the description of MDPDC SLOW_PD that it should be set the same as memory (which makes sense). Would you agree that the spreadsheet/script fails to do this? Do you have any recommendations on if the values should be set to fast precharge PD or slow?
Thanks for your question!
For 1, we had checked and confirmed bit16 isn't used. so no impact whether you set it or not.
In the aid and FSL's reference script, it is set due to some history reason.
For 2, would you please rise a new DI for your question? (please @ me direct in new DI)
I need involve IP owner to check it.
I have the same problem, could you say in detail, what simulation tool should I use? And in "飞思卡尔i.MX6平台DRAM接口高阶应用指导-DDR3篇", I found the following descripiton:
"General speaking drive strength (DSE) and ODT should match the characteristic impedance of transmission line. Actual test report of trace impedance should be delivered by PCB vendor."
Does that mean I can get the paramters from our PCB vendor? Or I should use some simulation tool to measure the actual parameters of our board?
I have some other questions,please help to make clear:
1. What is " wait = on" in RealView.inc mean? Because our board use enable_wait_mode=off in bootargs, I just want to check if they have some relationship.
2. For i.Mx6Q board, if the DRAM works in the same way if we just use single cpu core(by set nosmp in boot parameters)?(DDR3 parameters are almost the same as FSL reference design(4*128Mb*16=1GB)). The reason why I ask this question is that our boards can work more stability when use single cpu core than use all 4 cpu cores, I want to check if this phenomenon have something to do with the DDR parameters we have used.
Thank you very much!
I believe test report by PCB vendor should be more precise than simulation.
For your Q1, it can be removed. stress test tool also ignore it.
For Q2, I suspect it is a system issue not related DDR script and stress test.
Please contact FSL FAE for the question.
Thank you very much, your answers are very helpful. I have asked my colleague to contact PCB vendor to get the report.
I still have some other questions to ask you, I am sorry to bring you so much troubles, thank you again.
Q1: I have compared the default script of DDR_Stress_Tester_V1.0.3 for i.Mx6Q and the auto generated script from Mx6DQSDL DDR3 Script Aid V0.08.xlsx, there are some differences as follows:
0x021b000c from 0x555A7975 to 0x54597955
0x021b0010 from 0xFF538F64 to 0xFF328F64
0x021b0030 from 0x005A1023 to 0x00591023
0x021b001c from 0x04088032 to 0x02088032
I read the datasheet, these registers are about time parameters of DDR device,may I konw why they changed,which are better? Or the default generated script from Mx6DQSDL DDR3 Script Aid V0.08.xlsx is not for FSL demo board?
Q2: I found that in default script of DDR_Stress_Tester_V1.0.3 the ODT should be 120ohm, because the 0x021b0818 is 0x00011117, but the 0x021b001c is 0x00048031, is it OK? As if I set ODT to 120ohm, in auto generated script the 0x021b001c is 0x00408031.
Q3: I found that in default script of DDR_Stress_Tester_V1.0.3, the default write leveling is
It seems not the auto calibration parameters, do I need to update these value using the auto calibration results?
Thank you very much!
It is complex to answer your first question, you can study Freescale i.MX6 DRAM Port Application Guide-DDR3 and find answer by yourself.
For Q2, using 120ohm on FSL reference design is a power consumption balance. and you also can get hints through above guide.
For Q3, suggest do write leveling calibration and apply them into your script.
About Q1, I will study Freescale i.MX6 DRAM Port Application Guide-DDR3 more deeply, I want to know if those registers should be tuned manually?
About Q2, I have seen that using 120ohm is a balance, I just can't understand why 0x021b001c is 0x00048031, not 0x00408031, if I set ODT to 120ohm in Mx6DQSDL DDR3 Script Aid V0.08.xlsx, the auto generated value is 0x00408031, in 44.12.9, I did not find the answer.
About Q3, I will use the auto calibration values.
Thank you very much !
For Q2, Please also study the guide, you will find answer.
JESD79-3 should be referred.
Hope that will help you.
Last week we tested DDR singal of read mode. The value of tDQSQ-Diff is 235.14ps and that’s more than the high limit 200ps found to fail.
But the communication between the CPU(I.MX6S) and DDR3 is normal now. For CPU, this one even if NG, is no effect on communication, can we think so?
Hi Mr. Wang,
Your question is out of range of this topic/page covering.
Please ask it in a new DI.
Thank you for your kindly suggestion.
thanks for the useful Excel script.
i would like to make some small changes to the comments in the "RealView .inc" tab but it its write protected. When I try to remove the write protection, Excel asks me a password. let it empty does not work.
May you please give me the password?
Thanks in advance,
Sorry, I can't provide it to you for version control.
You can send your suggestion to me, i will change it in next version if it is reasonable.
Hope getting your understanding!
uhmm, I don't understand what is the relationship with the pwd and the version control...
thanks for the update.
Could you please report what is new between V0.08 and V0.09?
Thanks in advance.