New PMIC to Support the i.MX6 Processor Family

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New PMIC to Support the i.MX6 Processor Family

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New PMIC to Support the i.MX6 Processor Family

The LTC®3676 is a complete power management solution for i.MX6, ARM Cortex processor systems. The LTC3676 features eight independent resistor-programmable voltage rails, with dynamic control and sequencing, in compact QFN and LQFP packages. These rails supply power to the processor core, SDRAM, system memory, PC cards, always on real-time clock (RTC), and a variety of other functions.

  • Quad I2C Adjustable High Efficiency Step-Down DC/DC Converters: 2.5A, 2.5A, 1.5A, 1.5A
  • Triple 300mA LDO Regulators (2 Adjustable)
  • DDR Power Solution with VTT and VTTR Reference
  • Pushbutton On/Off Control with System Reset
  • Independent Enable Pin-Strap and I2C Sequencing
  • Programmable Autonomous Power-Down Control
  • Power Good and Reset Functions
  • Dynamic Voltage Scaling
  • Selectable 2.25MHz or 1.12MHz Switching Frequency
  • Always Alive 25mA LDO Regulator
  • 10μA Standby Current
  • 40-Pin 6mm × 6mm × 0.75mm QFN and 48-Pin 7mm × 7mm LQFP Packages

Contact Linear Technology for further details (please note that this is a pre-release product; however, data sheets and ES samples are available from Linear Technology)


Gerard Velcelean at


Steve Knoth at

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Great PMIC!

Bluetechnix has built a custom System-on-Module for i.MX6 Q/D/DL/S with it.

A Linux device driver is also available that supports dynamic voltage scaling and i.MX6 suspend modes properly.

Harald Krapfenbauer


just for your information - Linear now has a beta driver for i.MX6 Boards available.

You may contact Gerard Velcelean ( or Thomas Seitz ( (for Europe).


We have gone through the PMIC  for i.MX6 and it looks very good for our application.

I have the following doubts to get clarified.

1. We are going to interface 4 DDR3 (x16 bit) chips to i.MX6.

DDR3 requires the following power supplies

1. 1.5V

2. 0.75V

As shown below, 1.5V is supplied by SW4 of LTC3676 and 0.75V is supplied by SW1.

From the datasheet, 1.5V of SW4 is connected to VDD & VDDQ of DDR3. 1.5V of SW4 is also connected to VDDQIN to generate 0.75V.

But VTTR (pin 9 of LTC3676) is connected to which pin of DDR3 memory?


Moreover I do not understand the following block diagram. VTTR is connected to both input and output of comparator. How it works?


Can you please help me in understanding this.


Karthik R

Hi Karthik,

I am copying our design manager for the LTC3676, Jeff Marvin, so that he can provide guidance.

What is your "regular" email address and we can respond to you there and then post the answer to the MX community.

Best Regards,

Gerard Velcelean

Linear Technology

Hello Karthik,

You have the right initial understanding of powering DDR3 with LTC3676-1. Your questions are mostly on VTTR.

VTTR of LTC3676-1 is an output that buffers ½ VDDQIN. The block diagram shows this buffer as an opamp in unity gain feedback where OUT (VREF) is also tied directly to the negative input of the amplifier forcing it to track the amplifier V+ input which comes from a precision resistor divider which creates ½ x VDDQIN.

For connections to the DDR3 chips here is what I can say.

Most DDR3 chips I am familiar with have VREF pins. As an example, I am looking at DDR3 from Micron, part# MT41J256M16. These devices have pins VREFCA (for control and address) and VREFCQ (for Data) voltage references. The pins are described on Page 20 of that datasheet, with electrical spec requirements shown on page 46. Both VREF pins should track VDD x .5 to within 1% (+/- 15mV).

One point that our simplified block diagrams do not show properly is that VTT does not usually connect to the DDR3 chips. It is used as the termination voltage and is connected only to termination resistors. VTT still must accurately track ½ VDDQ as the LTC3676-1 provides.

I hope this helps.

Jeff Marvin

Burlington Design Center Manager

Linear Technology

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Last update:
‎11-12-2012 10:22 PM
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