Hello,
To get the speed you are looking for it’s not that easy as there are several factors than can slow down the DMA functionality such as:
1. DMA needs an assert-acknowledge-transfer-deassert sequence for a complete transfer; DMA's internal logic requires some cycles to handle this complete sequence.
2. DMA trigger source may also delay some cycles.
3. DMA master may get postponed due to bus matrix arbiter.
The DMA itself is deterministic, the uncertainty is the AHB matrix arbitration, for example, if DMA and other bus masters try to access the same bus slave port (a block of memory or the same peripheral), this can downgrade determinstics.
To control DMA transfer data to/from GPIO port in a paced manner, you will need a periodic trigger source, such as using a timer's event.
Another thing to consider it’s that if you use multiple DMA, the DMA itself also need to time-multiplexing and channel priority controls which channel is first. However, even if a channel has higher priority, if DMA master is busy, the high priority channel still have to wait.
Regards,
Estephania
