How to make MKW01Z128 PTB0& PTB1 Drive Strength Enable?

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How to make MKW01Z128 PTB0& PTB1 Drive Strength Enable?

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tedwu1
Contributor III

I found the reference manual at page 274 it says that "

Drive Strength Enable
This field is read-only for pins that do not support a configurable drive strength.
Drive strength configuration is valid in all digital pin muxing modes.
0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output."

I want to know how to make MKW01Z128 PTB0& PTB1 Drive Strength Enable?

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estephania_mart
NXP TechSupport
NXP TechSupport

Hello,

There is a register that need to be set in order to use the drive strength . Please check the Chapter 7 Port Control and Interrupts (PORT) of the reference manual.

pastedImage_1.png

Please check page 274 of the RM for further information.

Regards,

Estephania

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tedwu1
Contributor III

I read the registers of PORTB_PCR0 and PORTB_PCR1. Their value are 0x305, so the DSE is 0. I write the "1" to this bit and read the registers, the I got 0x345. But the RM says "This field is read-only for pins that do not support a configurable drive strength". Is it effective when I write the "1" to this bit? I want these two ports to high current
drive.

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estephania_mart
NXP TechSupport
NXP TechSupport

Hello,

The pins you are looking to use the drive strength in those pins it would  seem to be possible as the oens you are trying to use have that capability.

Could you please share how are you configuring it ?

Just to confirm, did you enable the clock gating ?

Regards,

Estephania

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tedwu1
Contributor III

I use these pins as PWM output and I configuring them as follows. Is they correct?

void TPM1_Init(void)
{
/* enable clock */
SIM_SCGC6 |= SIM_SCGC6_TPM1_MASK;
SIM_SCGC6 |= SIM_SCGC6_TPM2_MASK;

/* pin MUX configuration */
PORTB_PCR0 &= ~PORT_PCR_MUX_MASK;
PORTB_PCR0 |= PORT_PCR_MUX(3);

PORTB_PCR1 &= ~PORT_PCR_MUX_MASK;
PORTB_PCR1 |= PORT_PCR_MUX(3);

PORTB_PCR2 &= ~PORT_PCR_MUX_MASK;
PORTB_PCR2 |= PORT_PCR_MUX(3);
}

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estephania_mart
NXP TechSupport
NXP TechSupport

Hello,

Sorry abou this, but the help you need it's in configuring your coplete PWM setup? The problem you are having it's in your PWM configuration or just when you are trying to enable the drive strength? Because in that initialization you have you are not setting for modifying anything of the DSE field. Where are you setting that field?

Regards,

Estephania

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tedwu1
Contributor III

The code as follows. The function of Init_LF_125kHz is for initializing 125KHz. Manche_0_base for sending 52us 125KHz then staying low 52us (9600bps data). Manche_1_base for staying low 52us then sending 52us 125KHz. 

Previous half cycle in the function of Manche_0_base or Manche_1_base and last half cycle in the interrupt function of LF_TX_HalfTdataInt.

#define MOD_125KHZ 0x00C0
#define HALFMOD_125KHZ 0x0060

void Init_LF_125kHz(void)
{
TPM1_MOD = MOD_125KHZ;
TPM1_C1SC = 0x24;
TPM1_C0SC = 0x28;
TPM1_C1V = HALFMOD_125KHZ;
TPM1_C0V = HALFMOD_125KHZ;
}

void Manche_0_base(void)
{
TPM1_SC = 0x88; //Output 125kHz, select TPM1 clock source = bus clock; TPM1 begins.
TPM2_SC = 0x88; //1 bit begin bus clock devided by 1
while(!(TPM2_SC & 0x80)); 
TPM2_SC = 0x80;//disable TPM2
}

void Manche_1_base(void)
{
Init_LF_125kHz();
TPM1_SC = 0x80; //No Output
TPM2_SC = 0x88; //1 bit begin
while(!(TPM2_SC & 0x80));
TPM2_SC = 0x80;//disable TPM2
TPM1_SC = 0x80; //125KHz end
}

/* TPM2ch0 ISR, interrupt occurred at the middle point of a bit */
void LF_TX_HalfTdataInt(void)
{
if(TPM1_SC & 0x08)
{ //Manchester 0
TPM1_SC = 0x80;
}
else
{ //Manchester 1
TPM1_SC = 0x88; //output 125KHz
}
TPM2_C0SC |= 0x80; //Clear CHF
}

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estephania_mart
NXP TechSupport
NXP TechSupport

Hello,

 I see that you are using the TPMs software example, I'm not sure on if this it's possible due to the configurations of the project.

Still, have you tried  the following?

PORTB_PCR0 |= PORT_PCR_DSE_MASK;
PORTB_PCR1 |= PORT_PCR_DSE_MASK;

Regards,

Estephania

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tedwu1
Contributor III

Yes, I have tried them. but the data sheet says "Drive Strength Enable
This field is read-only for pins that do not support a configurable drive strength". I am not sure the settings are effective or not.

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estephania_mart
NXP TechSupport
NXP TechSupport

Hello,

But you cna also see this in the reference manual :

pastedImage_1.png

If you are using the ones with high drive, it is applicable.

Regards ,

Estephania

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