Deep-Power-Down-IO takes more current during the Power-Down

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Deep-Power-Down-IO takes more current during the Power-Down

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HarishCS
Contributor II

I am using a Qn9090 board for our application. My Goal is to enter into the Low Power Mode During the Inactivity . 

In my board , I tried Deep-Powerdown and the configured the wake up source as Reset Pin, at that time the board only takes the 2.6uA.

But When using the Deep-PowerDown-IO , the board takes about 2mA during the Deep Power-Down.At this time i Configured the PIN 17 which is user-button, also tried changing the PIN , Issue persists

Not Sure the Reason Behind such high current during the Deep-Power-Down-IO.

I Tried this using the SDK Example low-power-modes

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HarishCS
Contributor II

During Deep - power down ,RST  as wakeupsource what is the state of the Pins.

During Deep - power down ,IO  as wakeupsource what is the state of the Pins.

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Christine_Li
NXP TechSupport
NXP TechSupport

Hi, @HarishCS 

During Deep - power down ,RST  as wakeup source what is the state of the Pins.

==> I think the Pins are powered off. 

During Deep - power down ,IO  as wakeup source what is the state of the Pins.

==> I think the Pins are powered off except the wakeup source IO.

And as I mentioned before, in our datasheet the Deep-power-down power consumption is only 250nA (0.25uA), but you tested is 2.6uA. So I think there should be some problem in your hardware side that your board is not totally enter deep-power-down mode.

Can you please remove SPI to test again? What else did you change on your board?

Firstly we have to confirm the Deep-power-down mode (with only RST as wakeup source) has correct power consumption.

Then we continue to check the Deep-power-Down-IO mode.

 

Best regards,

Christine.

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Christine_Li
NXP TechSupport
NXP TechSupport

Hi, @HarishCS 

To better understand, I paste the Deep power down mode explanation copied from data sheet for your reference.

Deep Power-down mode shuts down virtually all on-chip power consumption, but requires
a significantly longer wake-up time. For maximal power savings, the entire system (CPU,
memories and all peripherals) is shut down except for the PMU. Wake-up is possible from
reset, NTAG field detect, and optionally GPIO. On wake-up, the part reboots.

Best regards,

Christine.

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HarishCS
Contributor II

During Deep Power Down RST, the board current is 2.6uA, which is fine because we have an accelerometer, several pull-ups and another module connected through SPI.

But During the Deep-PowerDown-IO, the Current consumption is 2mA, we don't the exact reason for this behaviour, do during the Deep-power-down-IO the pins states are TriStated or they are in some default state, or in some other state?

And Also during the PowerDown-RAM retention, all the pins are being handled(handled in the sense they are being put to appropriate modes like pull-up, pull-down, open-drain) before power-down, and the board current was 7.5uA.

 

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Christine_Li
NXP TechSupport
NXP TechSupport

Hi, @HarishCS 

Thanks for your feedback, then can you please share your hardware design to us? I also created an internal ticket to ask help from our internal team.

We prefer to know how connections on your side then check further.

 

Best regards,

Christine.

 

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Christine_Li
NXP TechSupport
NXP TechSupport

Hi, @HarishCS 

Do you find the root cause?

Can you please share your hardware connections to us(If it is not convenient to share on the community, you can send me by e-mail.)?

By the way, can you please check after disable/remove SPI? I suspect that the SPI has some applications not enter deep power down or current leakage.

At the same time, I also created internal case to ask help from our internal team.

Best regards,

Christine.

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HarishCS
Contributor II

Hello   @Christine_Li 

Can you Please Share your Email-ID,

Actually, SPI is being Connected to an other module, we also suspect that there is a leakage current, that is causing the 2mA since In DPD-IO, we couldn't Retain the GPIO Condition. 

Initially, what we assumed was During the Deep Powerdown IO, we are configuring only one Pin as Wakeup Source, so what we assumed is that other pins should not source or sink any current.

But During the Power-Down Ram Retention, I am Configuring the GPIO to appropriate Low Power Mode, Retaining those Register and using Syscon->retention register. In Powerdown it is just 10uA

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Christine_Li
NXP TechSupport
NXP TechSupport

Hi, @HarishCS 

I have sent one email to you, can you please check your email inbox?

Then you can reply to me directly if this issue is still not resolved because I saw that you have accepted my last answer as a solution.

 

Best regards,

Christine.

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1,206 Views
Christine_Li
NXP TechSupport
NXP TechSupport

Hi, @HarishCS 

Would you mind to let me know you SDK version? And which project are you using?

From my SDK:SDK_2_6_205_QN9090DK6, I didn't find this example project: low-power-modes.

Do you use in BLE scenario?

 

Best regards,

Christine.

 

1,198 Views
HarishCS
Contributor II

Hi @Christine_Li 

SDK Version 2.6.5

Example Project is :/driver_examples/powerdown_demo

In our Board , we have SPI line to connect to Accelerometer, Since the SPI is now unhandled does it takes high current.

How should I handle the GPIO Pin before going to deep-power-down

No I Dont Use BLE .

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Christine_Li
NXP TechSupport
NXP TechSupport

Hi, @HarishCS 

I checked the User Manual of QN9090, the consumption will changed according to how many times you pressed the user interface button. It will change to different mode.

1.Please confirm to enter DPD-IO (deep-power-down-IO) mode because it may change to Sleep mode, the currents will be 1.9mA or Rx Idle mode, the current will be 2.4mA.

2.Can you please also have a try without SPI line?

 

Best regards,

Christine.

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1,140 Views
Christine_Li
NXP TechSupport
NXP TechSupport

Hi, @HarishCS 

Thanks for your feedback.

I will have a try on my local side, then keep you posted here with any updates.

 

Best regards,

Christine.

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