Hi,
But if you are trying to lock the gate3 should not be the 0x1000 the correct value?
Yes, i also thougth that 0x1000 should be the correct value, but then i found this code in the Timesys BSP (core_mutex_sema4.c):
#if PSP_MQX_CPU_IS_VYBRID
static const int idx[16] = {3, 2, 1, 0, 7, 6, 5, 4, 11, 10, 9, 8, 15, 14, 13, 12};
#else
static const int idx[16] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15};
#endif
....
// Enable 'unlocked' interrupt for this core
if (_psp_core_num()==0) {
component_ptr->DEVICE[core_num].SEMA4_PTR->CP0INE |= 1 << (SEMA4_NUM_GATES - 1 - idx[mutex_num]); //1 << (SEMA4_NUM_GATES-1-mutex_num);
} else {
component_ptr->DEVICE[core_num].SEMA4_PTR->CP1INE |= 1 << (SEMA4_NUM_GATES - 1 - idx[mutex_num]); //1 << (SEMA4_NUM_GATES-1-mutex_num);
}
i used the same in my code. So thats why the register value is 0x8000 for Gate 3. This Code Works, since the Interrupts coming through correctly from FreeRTOS to Linux.
I just describe you my debugging steps:
1. check if the NVIC_ISER0 value is correct:
0xE000E100: 0x0010
2. lock Gate 3 on linux side
SEMA4_Gate03 0x01
3. initialise the Sema4 on FreeRTOS side and check the SEMA4_CP1INE register:
x/1w 0x4001D048
0x4001D048: 0x80000000
4. try to lock the gate on FreeRTOS side
5. unlock the Gate on linux side and check the CP1NTF register value:
x/1w 0x4001D088
0x4001D088: 0x80000000
6. Check the pending Intterupt register of the NVIC:
x/1h 0xE000E200
0xE000E200: 0x0000
7. Check the Interrupt Active Bit Register, NVIC_IABR0:
x/1h 0xE000E300
0xE000E300: 0x0000
So the Interrupt is not pending, but the values of the SEMA4_CP1NTF and SEMA4_CP1INE registers are correct.
By the way i'm wondering why the RM states that the offset to the SEMA4_CP0INE Register is 40, but when i take a look at the SEMA4_MemMap struct in the "MVF50GS10MK50.h" the offset is 42?:
/** SEMA4 - Peripheral register structure */
typedef struct SEMA4_MemMap {
uint8_t GATE[16];
uint8_t RESERVED_0[50]; /* 48 */
uint16_t CP0INE; /**< Semaphores Processor n IRQ Notification Enable, offset: 0x40 */
uint8_t RESERVED_1[6];
uint16_t CP1INE; /**< Semaphores Processor n IRQ Notification Enable, offset: 0x48 */
uint8_t RESERVED_2[54];
uint16_t CP0NTF; /**< Semaphores Processor n IRQ Notification, offset: 0x80 */
uint8_t RESERVED_3[6];
uint16_t CP1NTF; /**< Semaphores Processor n IRQ Notification, offset: 0x88 */
uint8_t RESERVED_4[118];
uint16_t RSTGT; /**< Semaphores (Secure) Reset Gate n, offset: 0x100 */
uint8_t RESERVED_5[2];
uint16_t RSTNTF; /**< Semaphores (Secure) Reset IRQ Notification, offset: 0x104 */
} volatile *SEMA4_MemMapPtr;
Best Regards
Simon
