Hello community,
On NOTE of Figure 32. QuadSPI Input/Read timing (DDR mode) in datasheet VF3xxR, VF5xxR, Rev. 8, 01/2018, it say that
• The numbers are for a setting of 0x1 in register QuadSPI_SMPR[DDRSMP]
• Read frequency calculations should be: Tck/2 > (flash access time) + Setup (Tis) - (QuadSPI_SMPR[DDRSMP])x Tck/4
• Frequency calculator guideline (Max read frequency): Tck/2 > (Flash access time)max + (Tis)max - (QuadSPI_SMPR[DDRSMP]) x Tck/4
• Hold timing: flash_access (min) + flash_data_valid (min) > Tck/2 + HOLD(Tih) + (QuadSPI_SMPR[DDRSMP])Tck/4
But Figure 30-422. DDR sampling edges of Vybrid Reference Manual, Rev. 5, 06/2014 or
Figure 10-25. 4x sampling edges in DDR mode of VFxxx Controller Reference Manual, Rev. 8, 11/2015,
It seems that step of QuadSPI_SMPR[DDRSMP] is Tck/8
• The numbers are for a setting of 0x1 in register QuadSPI_SMPR[DDRSMP]
• Read frequency calculations should be: Tck/2 > (flash access time) + Setup (Tis) - (QuadSPI_SMPR[DDRSMP])x Tck/8
• Frequency calculator guideline (Max read frequency): Tck/2 > (Flash access time)max + (Tis)max - (QuadSPI_SMPR[DDRSMP]) x Tck/8
• Hold timing: flash_access (min) + flash_data_valid (min) > Tck/2 + HOLD(Tih) + (QuadSPI_SMPR[DDRSMP])Tck/8
How do you think about time period of QuadSPI_SMPR[DDRSMP]?
Best regards,
Ishii.
