Hi, I'm bringing up our T1040(Part number:NXE7MQB) board based on T1040RDB.
I have some question as following:
1.How to write Clocking_CLKPCSR register with PBI? I want to enable clk_out pad to confirm my pll set in RCW.
2.According to our T1040 Part number, The main freq is 1200MHz and the Die revision is 1.1. I get default RCW
and u-boot.bin from SDK 1.7,but the main freq is 1400MHz in SDK1.7 RCW. So I rebuild the RCW with QCVS,
Do I need to rebuild the u-boot since the main freq is differrnt?
3.I use CW10.4 and QCVS 4.2.1 to build the PBL.bin(for SD boot) acording to "QorIQ-SDK-1.7-IC-RevB.pdf"
Chapter 9.1.5 Generating the PBL image.
There is a step as following:
• Insert the u-boot image file:
Select ACS File (data from binary file) then file Browse appears.
For T4240/T2080 SoCs:
Change offset: 0xfd000 (will change to 0xfd8000 if U-boot version is 2014.04+)
Browse to File: u-boot-spl.bin
Hit the Add button, then the Apply button
but I cann't find out the menu "Insert the u-boot image file" "Select ACS File (data from binary file)",
Maybe the QCVS 4.2.1 is different,Please tell me the corresponding menu operation in QCVS4.2.1, Thanks.
Regard.
1) Add the following PBI instruction:
09000A00 <value of the CLKPCSR>
2) It is not needed to rebuild U-Boot.
3) It is recommended to use SDK v1.8 or later where complete SD image is generated.
Hi, ufedor
Thanks very much.
Now we have new issue as following:
We can set up a connect CW bareboard project to access t1040's registers, but we cann't set up a
Download CW bareboard project to run. The error message is :
Would you please give some Hints?
Try to use "..._SRAM_T1040_Download" debug configuration.
Hi, ufedor
Thanks a lot.
we can set up a Download RAM CW bareboard project now, and uart1 can print correctly. The reason is the default ddr3l init script does not work
with our board.
There are only SPI flash(the part is same as t1040rdb) and SD socket on Our t1040 board. I have burn RCW to SPI flash with CW Tap, and set board to read RCW from SPI flash. I think it does work since I can found the ASLEEP pad is low after power up the board. If we erase the SPI flash, the ASLEEP pad is high after power up the board.
Accroding your description. We build the complete SPI u-boot BIN(RCW+PBI+U-BOOT-SPL+U-BOOT). and burn it to SPI flash, but it does not work. The
ASLEEP pad is high after power up the board, and uart1 output nothing. We have upgrade the RCW in the U-BOOT source code. It seems u-boot can read SPD(we use so-dimm in our board) and init the DDR3L automaticlly, does it? By the way, we use SDK ver1.7, because SDK ver1.8+ only support DDR4.
I think the different of T1040RDB and out board is:
U-DIMM(2G) SO-DIMM(2G)
NOR flash boot SPI/SD boot
seperate sys(100M) and ddr(66M) clk single sys ddr clk soruce(100M)
Would you please give some hints to adjust the u-boot source code accordingly?
It is convenient to create new community question or Technical Case for your last request.
Hi ufedor,
Thanks a lot
I have created a new case.