Running on a T1024 board with vxWorks7 as the OS and setting up the e5500 watchdog timer for processor reset only and no interrupt operation. I have written an interface to the vxbFslBookeTimer and vxbFslBookeWDTimer drivers provided as well as modified the drivers for proper operation. The desired operation is when the watchdog timer expires fully a RESET_REQ is signaled off processor to a CPLD which performs the PORESET or HRESET of the board. I have fully tested the operation of my interface and the driver and it works but there is one caveat.
Starting with the board powered off.
If the board is powered on and the system completely loads and the watchdog timer gets configured but on expiration a reset does not occur. When I say the timer gets configured I am able to read back the TCR register with the correct settings and the vxbFslBookeWDTimer driver that is allocated and attached to the watchdog timer. If I change this operation by one simple step then the watchdog timer operates correctly. See below.
Starting with the board powered off.
If the board is powered on and I break it down to the simplest operation possible by stopping the power up sequence at the U-Boot prompt then I perform a "reset" at the U-Boot prompt which in turn causes U-Boot to again run and the processor to reset. The key here is the processor was reset while powered on. Then I allow the system to completely load and the watchdog timer gets configured and after it expires the system resets successfully.
Conclusion:
So keeping it as simple as possible if I do not run my interface and the vxbFsl driver code I simply Power on the board and then reset the processor after the board is powered on the watchdog timer works and continues to work after each subsequent reset. If I power off the board and back on but do not perform a second processor reset the watchdog timer RESET_REQ does not appear to get off processor to the CPLD for proper reset operation. The watchdog timer will not work unless I reset the processor while the board is powered on and if I do so then the watchdog timer works correctly.
Update:
Was able to remove the watchdog timer driver from the system. At the U-Boot command prompt I was able to get to the CCSBAR registers. In particular in the T1024RM.pdf the 7.3.13 Reset Control Register(DCFG_CCSR_RSTCR). Address: E_0000h base + B0h offset = E_00B0h
Bit 30 states as follows:
RESET_REQ
Hardware reset request. External hardware may then decide to issue the desired reset signal
(PORESET_B or HRESET_B) to the device.
0 No reset request initiated.
1 Hardware reset request initiated by software.
Two different scenarios: 1) power on the board and stop at the U-Boot command prompt. 2) power on the board and stop at the U-Boot command prompt perform a reset at the U-Boot command prompt and again stop at the U-Boot command prompt.
We performed a mm.l 0xFFE0E00B0 at the U-Boot command prompt and set the RESET_REQ bit to a 1.
In scenario 1) the bit was set but the CPLD does not PORESET or HRESET the board. We were able to readback the register and see the bit is set but we believe the processor is not sending the RESET_REQ off processor to the CPLD.
In senario 2) the bit was set and the board was reset by the CPLD.
