I am writing a bare metal NOR flash driver for the T1040RDB board.
I planned to use IFC page read mode (IFC_CSORn_NOR.PGRD_EN = 1) in order to speed up data reading through DMA, but once activated, I observe a few errors when reading single data.
The problem comes while controlling erasing operation: after launching the erase sector operation, I have to read words at any flash address (but always at the same address), until a specific status bit stop toggling, signaling end of erasing.
A typical toggling sequence is: 0x48 0x08 0x48 0x08 0x48 0x08…
When error occurs, the sequence is e.g.: 0x48 0x08 0x48 0x48 0x08 0x48…
Thus it seems that sometimes (approx. once every 20000 read), when 2 single read accesses are made consecutively, there is only one effective bus transaction, so the same value is reported twice to core bus.
Is it a known behavior? Can it be another problem?
For PGRD_EN = 1, RM says: Software should issue transaction based on device page size
So I wonder if it is a mandatory requirement? (should “should” be “must”?)
For information, the flash is accessed with a cache-inhibited and guarded TLB, and I use volatile data pointer.
Thanks for any information!
If there is difference between your device page size and NOR Flash device page size, the part of data can be omitted or duplicated. You software should proceed this problems.
There is no similar problem if correct page size is used.
It looks like that Page Read mode cannot be used for DQ6 toggling reading. The DQ6 toggle reading using the system may use either OE# or CE# to control the read cycles. The Page Read mode asserts the CE# for full page reading.
Thanks for your answer.
So, you think that 2 consecutive single accesses e.g. :
read1 = *(volatile T_UINT16 *)NOR_BASE_ADDRESS;
read2 = *(volatile T_UINT16 *)NOR_BASE_ADDRESS;
could assert OE# and CE# only once, right ?
You're probably right, anyhow, it is very odd that the problem appears only once every 20000 read (on average).