Problem in connections of IFC

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Problem in connections of IFC

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faizmajeed
Contributor III

Hi

I am using T1042 processor and trying to interface 3 NOR Flashes with IFC.
1 for booting

2 application flashes

i have select "Mode 0 pin muxing (CSORn[ADM_SHFT_MODE] = 0)" and have some confusion about address shifting scheme. and i am using nor flash which uses (A0 to A26) addresses.

i have three queries about using this all

1) what value should i select in CSORn[ADM_SHFT] register

2) what value should be selected in Reset configuration word (RCW) [cfg_rcw_src [0]_[1:4]_[5:8]
value]

3) which pins can i use for write protect for each chip select

4) which pins can i use for ready/busy 

i am really confused in shifting mechanism of above mentioned two registers.

Do you have any suggestion ?? 

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1 Solution
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r8070z
NXP TechSupport
NXP TechSupport


Have a great day,

The IFC write protect pin is not for NOR flash. Using Ready/Busy# pins also is not mandatory. Ready/Busy status can be detected by reading flash device status register. Also you can use IFC_RB1 for device connected to IFC_CS1 and IFC_RB0 for both NOR flash devices connected to IFC_ CS0 and to IFC_CSx (x from 2,3…7) by wired OR. In these case IFC_RB[2:7] is not needed hence you can set RCW[IFC_GRP_A_BASE]=0 and RCW[IFC_GRP_B_BASE] =0 making available IFC_A[25:27] and IFC_A[28:31] signals. I.e. you can use 32 bit address mode. When for ADM_SHFT_MODE=0 IFC_A[16:31] provide 16 least significant address bits. During address phase IFC_AD[0:15] provide the rest 16 most significant address bits of the 32-bit address while there is not shift (ADM_SHFT=0). These bits should be latched. For 8-bit NOR flash you should connect
 IFC_A[31:16] -> A[0:15]
 IFC_AD[15:5] -> latch -> A[16:26]

For 16-bit NOR flash you should connect
 IFC_A[30:16] -> A[0:14]
 IFC_AD[15:4] -> latch -> A[15:26]

The cfg_rcw_src [0]_[1:4]_[5:8] and RCW[IFC_MODE] you can see in the manual’s Table 4-6. RCW source encodings. We should set cfg_rcw_src[5]=0 and cfg_rcw_src[6:7]=11. 

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241 Views
r8070z
NXP TechSupport
NXP TechSupport


Have a great day,

The IFC write protect pin is not for NOR flash. Using Ready/Busy# pins also is not mandatory. Ready/Busy status can be detected by reading flash device status register. Also you can use IFC_RB1 for device connected to IFC_CS1 and IFC_RB0 for both NOR flash devices connected to IFC_ CS0 and to IFC_CSx (x from 2,3…7) by wired OR. In these case IFC_RB[2:7] is not needed hence you can set RCW[IFC_GRP_A_BASE]=0 and RCW[IFC_GRP_B_BASE] =0 making available IFC_A[25:27] and IFC_A[28:31] signals. I.e. you can use 32 bit address mode. When for ADM_SHFT_MODE=0 IFC_A[16:31] provide 16 least significant address bits. During address phase IFC_AD[0:15] provide the rest 16 most significant address bits of the 32-bit address while there is not shift (ADM_SHFT=0). These bits should be latched. For 8-bit NOR flash you should connect
 IFC_A[31:16] -> A[0:15]
 IFC_AD[15:5] -> latch -> A[16:26]

For 16-bit NOR flash you should connect
 IFC_A[30:16] -> A[0:14]
 IFC_AD[15:4] -> latch -> A[15:26]

The cfg_rcw_src [0]_[1:4]_[5:8] and RCW[IFC_MODE] you can see in the manual’s Table 4-6. RCW source encodings. We should set cfg_rcw_src[5]=0 and cfg_rcw_src[6:7]=11. 

-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

View solution in original post

240 Views
faizmajeed
Contributor III

Thank you for your response and you well explained all the problems,

Now just i have little more confusion

1) Like addresses, Data will also be reversal e.g AD[0:15] --> D[15:0] ??

2) what should i connect to write protect of NOR Flash ?

3) Can i interface NVRAM with IFC using its GPCM mode ?

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