Why MMA9555 's Pin1 ID is shortened to Pin1?

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Why MMA9555 's Pin1 ID is shortened to Pin1?

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wenxue
NXP Employee
NXP Employee

Hi everybody,

I found MMA9555's Pin1 ID is shortened to Pin1. Actually the resistor between them is 0.3Ω. Do you know what's the reason?

I don't find any description about Pin1 ID in datasheet. Generally speeking, this pin should be just an identification. I don't understand why it connect to VDD.

9555.png

MMA.png

Any comments would be appreciated.

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JackITB
NXP Employee
NXP Employee

Hi Wenxue,

This is due to the layout of device package substrate: pin 1 ID is connected to pin 1 through the bottom layer of this LGA substrate.

Datasheet provides footprint and land pattern information which keep pin 1 ID unconnected. Did you experienced any issue when mounting the part ?

Regards,     Jacques.

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564 次查看
JackITB
NXP Employee
NXP Employee

Hi Wenxue,

This is due to the layout of device package substrate: pin 1 ID is connected to pin 1 through the bottom layer of this LGA substrate.

Datasheet provides footprint and land pattern information which keep pin 1 ID unconnected. Did you experienced any issue when mounting the part ?

Regards,     Jacques.

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wenxue
NXP Employee
NXP Employee

Hi Jacques,

Yes, a customer meet an issue when mounting the part. Customer designed a pad in the bottom of the chip, and the pad is connected to GND. So Pin1 VDD is shortened to GND in this case.

Datasheet don’t have any information indicate Pin1 ID is shortened to GND. I think we need describe it clearly.

Best Regards,

Wenxue

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JackITB
NXP Employee
NXP Employee

Hi Wenxue,

I'm surprised the customer introduced a GND pad under the package.

Figure 14 and 13 in Datasheet are providing clear description of solder mask and stencil opening.

Anyway, we'll add a word of caution about pin 1 ID in a subsequent revision of the datasheet.

Thanks for raising this concern,     Jacques.

MMA955xL recommended footprint.jpg

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