VDD Sensitivity of MMA8451Q

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VDD Sensitivity of MMA8451Q

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bsmith
Contributor I

The MMA8451Q datasheet specifies a 'nominal' VDD supply voltage of 2.5V.

I wonder if anyone knows what effect a different supply voltage might have on this device? Would it have an effect on the offset? or on the sensitivity? Many other accelerometers specify these values.

Our application is battery powered, so the supply voltage, if unregulated, would drop steadily during the life of the product. Also, how sensitive is the MMA8451Q to noise on the VDD supply?

Thanks in advance!

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TomasVaverka
NXP TechSupport
NXP TechSupport

Hi Bryn,

Both the offset and sensitivity parameters are mainly related to the MEMS and package characteristics as the analog content and offset and trim algorithms embedded in the ASIC are designed for a VDD voltage range of 1.95V to 3.3V. So it means that there is no change in those parameters when operating at a different supply voltage within this range.

Voltage ripple can affect the MMA8451Q performance for frequencies close to the digital clock frequency. For ripple frequencies less than 10kHz, there is no performance degradation due to good power supply rejection of the internal regulators. Generally, a 4.7uF capacitor is recommended to adequately decouple the accelerometer from noise on the power supply as shown in Figure 4 of the data sheet.


Regards,

Tomas


PS: If my answer helps to solve your question, please mark it as "Correct" or “Helpful”. Thank you.

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1,060 次查看
TomasVaverka
NXP TechSupport
NXP TechSupport

Hi Bryn,

Both the offset and sensitivity parameters are mainly related to the MEMS and package characteristics as the analog content and offset and trim algorithms embedded in the ASIC are designed for a VDD voltage range of 1.95V to 3.3V. So it means that there is no change in those parameters when operating at a different supply voltage within this range.

Voltage ripple can affect the MMA8451Q performance for frequencies close to the digital clock frequency. For ripple frequencies less than 10kHz, there is no performance degradation due to good power supply rejection of the internal regulators. Generally, a 4.7uF capacitor is recommended to adequately decouple the accelerometer from noise on the power supply as shown in Figure 4 of the data sheet.


Regards,

Tomas


PS: If my answer helps to solve your question, please mark it as "Correct" or “Helpful”. Thank you.

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bsmith
Contributor I

Thanks Tomas for your detailed and helpful answer.

The datasheet mentions a VDD range of up to 3.6V, but in your answer you mentioned that the algorithms in the ASIC are designed for 1.95 - 3.3V. Does that mean that it might be worth ensuring that limit VDD to a maximum of 3.3V for improved accuracy?

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TomasVaverka
NXP TechSupport
NXP TechSupport

No, it should have been written 3.6V, sorry for my mistake, Bryn.

Regards,

Tomas

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