Scheck swt fail

[Junjie]

Hi Teams

     Customer's  application based on saf version 1.0.0 and Rtd 2.0.1. Customer fix Scheck scheck swt bug manually according to the  latest saf version. In sCheck_Swt_CounterTestRun , found that when set TO to 0x20 can pass test and then set TO to 0x10 can not pass test. but out of test loop, after disable swt in scheck. IR in swt is set and interrupt pending in core. and then after scheck, customer reconfigure swt, swt is dysfunction that the action of swt is not consistent with configuration. But this issue could not be reproduced by simple demo code.

customer wants to know:

• Ask which scenario will cause the test to fail.
• Customer wants to know the root cause of scheck swt fail.

Best Regards

Junjie

[JonasStyskala]

The issue was tracked down to hardware of SWT. New errata is being reviewed at the moment. Once the errata is published SAF sCheck team will implement necessary workaround for future SAF releases.

[JonasStyskala]

Hello Junjie,

the timing is crucial for this test. Clock of the SWT counter is SIRC (32 kHz). The execution loop contains wait cycle with wait timeout. This wait timeout is computed based on 10 SWT cycles. The 10 SWT cycles are transformed to STM timer ticks. Using a configuration tool (e.g. Tresos) user configures STM instance available for sCheck module to be used. User also configures what is STM frequency, which the user needs to set in hardware.

In case that wait loop takes longer (e.g. due to incorrect frequency configuration of STM) an interrupt might occur and test fails. The slightly different value configured in Tresos vs HW might cause latest iteration of the test to fail, because latest iteration is most precise.

I was able to simulate following case:

Test is passing successfuly, but at sCheck_Swt_CounterTestRestore() function there is IRQ 42 pending in the core. I was able to simulate this beahvior which is probably similar to your experience by incorrect configuration of sCheck (STM frequency in Tresos).

Can you confirm that STM frequency is correct and configuration of sCheck matches with hardware?

[Junjie]

Hi @JonasStyskala 

We check with customer that the STM0 selected for scheck and 40MHZ as below 

Let's add more details about this case.

1. when keep 10(actually 17 count ) swt count wait time out, scheck test pass ,but customer reconfigure swt after shutdown scheck test, swt work in abnormal. actually in this swt count wait time out, Test should not pass when set TO to 0x10.right? so why we set this count to 10?

2. when modify swt count wait time out to 14(actually 21 count )scheck test pass ,customer reconfigure swt after shutdown scheck test, swt work in normal , but interrupt flag of swt  was cleared in the end of test but set after shut down scheck, 

3. when modify swt count wait time out to 17(actually 24 count )scheck test fail,customer reconfigure swt after shutdown scheck test, swt work in normal , interrupt flag of swt  was set in the end of test and also set after shut down scheck。

so there are 3 questions from customer:

1. when set swt count wait time out to 10. why reconfigure swt after shutdown scheck test, swt work in abnormal?

2. when set swt count wait time out to 14, why interrupt flag of swt was set after swt disable?

3. why we set wait time out to 10 in scheck swt?

Best Regards

Junjie

[JonasStyskala]

Hello @Junjie, here are answers for customer:

1. This needs to be clarified with HW team. I am working on that.
2. This configuration is probably caused by race condition between SWT counter and STM counter. The test disables SWT right at the time of interrupt flag getting set, but SWT to CPU ISR reporting is not finished in this time.
3. SWT timeout of 10 SWT cycles is set as longest timeout value which should not cause ISR to trigger. It is also sufficient timeout (with buffer) in which counter of SWT should change its counter value.

Could you provide detailed clocking details?

• CORE_CLK = ?
• AIPS_SLOW_CLK = ?
• SIRC_CLK = 32 kHz
• STM_0 = 40 MHz

Thank you, Jonas

[Junjie]

Hi @JonasStyskala 

    CORE_CLK=160M，AIPS_SLOW_CLK=40M

we have also reproduced this issue by simple demo as mentioned in teams. prerequirement: A/B HSE  framework installed, swt reconfiguration after shutdown scheck , then reset will be triggered right now (not based on swt configuration).

Best Regards

Junjie