SM1.DATA_ADDRESS_ECC and SM1.EDC_after_ECC Bus Fault and EIM clarifications

[FabioG]

Hi there,

I have some questions:

1)SM1.DATA_ADDRESS_ECC. s32k3xx, during memory access (address), the error
detected and not correctable, does trigger a bus fault error (forced hard-fault exception?) 

2)SM1.EDC_after_ECC. s32k3xx does EDC mechanism triggers a bus fault error  (forced hard-fault exception?) 

3) for EIM injection channel, I am not shure what EIM channels shuld be configured:

referring RM_rev8, pp1846,  50.1.2 "EIM channel Mapping", tab 264:  

4) does EIM channel 28 "ECC checking address" the one and only for EM.DATA_ADDRESS_ECC triggering? 

5)does EIM channel  29  "EDC checking write data" and 30 " EDC checking read data" the ones and only for   SM1.EDC_after_ECC triggering  ?

6) in order to trigger EIM injection on channel 28  for ECC_ADDR tests, a read/write access to SRAM0 and  read/write access SRAM1 should be done (or only to SRAM0 )is required , or other?

7) in order to trigger EIM injection on channel 29/30 for EDC tests, a read/write access to SRAM0 and  read/write access SRAM1 should be done (or only to SRAM0 )is required , or other?

Best Regards,

Fabio

[antoinedubois]

Hi Fabio,

1 and 2) Yes in most cases it should trigger a bus fault (because it actually read or write to an incorrect transaction where you may not have access) but in some cases it may not, and it will be capture by the NCF channel in FCCU. Then you can read the ERM to have more information. If such failure are observed in FCCU in general I would recommend system Reset as the impact is hard to predict.

3-7) EIM are really hard to configured properly as you are probably experiencing and the HW has much more flexibility as what you actually need for your design. That's why we provide the SAF Schecks library that takes the best use of EIM for the latent fault concept. I believe you can access an evaluation license to help you design it, and production license at a reasonable cost. I forwarded your detailed questions to the design team, but it may take few weeks before we get an answer.

[FabioG]

Hi Antoine,

Thanks for response,

I've already evaluated SAF 1.0.4 but sCheck latent faults related to EIM are not included there:

Only FCCU sCheck NCF examples are present in this package; and only EIM on SRAM0 and SRAM1 examples , by using single SPD drivers are present (see  related main.c and exeption.c). No sCheck management of EIM is present. So in our case, the evaluation licensed package is unuseful...

Best Regards

Fabio