FMEDA PIN FMEDA

[HeebeomPark]

In FMEDA, for the following example with PTA0, what are the difference between two capture?

The capture1 is more like inside of the circuit for PTA0 in the MCU.

Also the capture2 is the external interface , which is limited to Pin. 

My understanding is correct? 

Capture1

Also for Capture1, there are the failure modes. Can you also explain it more detail? I could guess however I need more explicit explain for each meaning of the failure mode. For example, floating, stuck , pull up, pull down are understandable however, Inadequate Drive Strength/Slew Rate and incorrect dynamic range are not understandable that needs more additional information/explain.  Also even understandable failure modes, we need further explain when those failure modes shall be used like input or only output and so on. 

And the above Capture1 is MCU dependent on which is not supposed to be covered by the mechanisms such as the following? I think application shall consider the failure modes and use proper safety mechanisms?

• SM4.COMM_SAFEPROT
• SM1.RED_PERI_PHY_SEP

The below is pin that is more relevant to application. 

Capture 2

[HeebeomPark]

The product is 32K388.

[Yashwant_Singh]

Hello Heeboem,

Please see some responses below:

• Yes capture 1 is about the failure modes of the on chip PAD(on the die) for PTA0 while capture 2 is about the failure modes of the PIN(on the package) for PTA0.
• You are also correct that the safety mechanism of the PADs/PINs depend upon their usage. For example if PTA0 is being used for LPUART communication then its failure modes would be covered via E2E.
• The failure modes that you highlighted which are the ones other than output stuck/floating are relevant to the PAD control logic governing the electrical characteristics of the pads present on the die. The SIUL2 module provides this control. Below are the explanations for some failure modes.:
  • Inadequate Drive Strength/Slew Rate: Electrical Properties of the PADs such as drive strength and slew rate can be controlled via the SIUL2 module. Inadequate drive strength or current flow through the PAD can cause an unintended state to be reflected on the pad/pins. Inadequate slew rate can limit the throughput for the communication peripherals using these PADs.
  • Uninteded pull up/pulldown register enable/disable: GPIO pads are provided with internal pull up/pull down registers. Unintended activation of these pull ups/pull downs can again cause an unintended state to be reflected on the PADs.
  • Incorrect dynamic range: This failure mode is only applicable for analog pads. Fluctuations in the signals being sampled beyond a certain range can cause corruption of the data being captured. However, the modelling structure of K3 family FMEDA doesn't differentiate among analog and digital PADs. This failure mode can be marked as safe for digital pads. This failure mode can be marked as safe for Digital Pads.

Hoping this helps.

Thanks!

-Yashwant

[antoinedubois]

Hello Mr. Park,

Can you please tell us which product you are referring to? THat will help me answer your question.