TRNG

cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
3,567 Views
vikmonti7804
Contributor III

HI ,

   I am looking for more information regarding the class of the TRNG but i am not able to find any document. I need detailed information regarding the class like DRG3 , DRG4 for TRNG so that i can know which one i have to use for the CMAC key generation.

Kindly provide me the document.

 

0 Kudos
1 Solution
2,940 Views
lukaszadrapa
NXP TechSupport
NXP TechSupport

Hi @vikmonti7804 

Working project is attached.

There were swapped parameters in GetRngNum. And I forced needed objects to noncacheable area.

Best Regards,
Lukas

View solution in original post

0 Kudos
24 Replies
3,449 Views
lukaszadrapa
NXP TechSupport
NXP TechSupport

Hi @vikmonti7804 

search for rngClass keyword in both HSE-B Firmware Reference Manual and also in S32K312_HSE_Service_API_Reference_Manual which can be found in HSE FW package.

lukaszadrapa_0-1709636543299.png

 

lukaszadrapa_1-1709636548579.png

 

Regards,

Lukas

0 Kudos
3,230 Views
vikmonti7804
Contributor III

Hi Lucas,

            I am trying to generate the Random number generation but its not working and giving back the response that the feature is not supported (HSE_SRV_RSP_NOT_SUPPORTED).

vikmonti7804_0-1710317896925.png

 

0 Kudos
3,216 Views
lukaszadrapa
NXP TechSupport
NXP TechSupport

This is caused by data cache, most likely. To confirm it, you can simply turn off the data cache and it should work. To solve it, all the data structures used for communication with HSE via MU need to be forced to non-cacheable memory.

Regards,

Lukas

0 Kudos
3,193 Views
vikmonti7804
Contributor III

HI Lucas,

           Can you please explain how to turn off this data cache?

And how to do all the data structures used for communication with HSE via MU need to be forced to non-cacheable memory ?

please explain with some images.

 

0 Kudos
3,173 Views
lukaszadrapa
NXP TechSupport
NXP TechSupport

Data cache can be disabled by DC bit in CCR ARM core register:
https://developer.arm.com/documentation/dui0646/b/Bhcjabhi

You can take a look at Crypto examples like:
c:\NXP\S32DS.3.5\S32DS\software\PlatformSDK_S32K3\RTD\Crypto_43_HSE_TS_T40D34M40I0R0\examples\S32DS\S32K3XX\Hse_Ip_AesEncAsyncIrq_S32K344\src\main.c

You can find something like this in the LOCAL VARIABLES section (there are more similar definitions for different type of objects):

lukaszadrapa_0-1710438456457.png

Regards,
Lukas

0 Kudos
2,901 Views
vikmonti7804
Contributor III

Hi Lucas,

        I did same as you suggested, please look into the images attached. But still its not wotking, kindly provide any working code or try at your end, kindly reply on urgent basis. I have also attached main file.I am working with IAR with A_B swap memory of HSE

response i am getting from the code below.

#define HSE_SRV_RSP_NOT_SUPPORTED               ((hseSrvResponse_t)0xAA55A11EUL)  /**< @brief The operation or feature not supported. */

vikmonti7804_0-1711015651494.png

 

vikmonti7804_1-1710994827105.png

vikmonti7804_2-1710995016711.png

 

0 Kudos
2,941 Views
lukaszadrapa
NXP TechSupport
NXP TechSupport

Hi @vikmonti7804 

Working project is attached.

There were swapped parameters in GetRngNum. And I forced needed objects to noncacheable area.

Best Regards,
Lukas

0 Kudos
3,120 Views
vikmonti7804
Contributor III

Hi Lucas,

Thanks for explaining but why these points are not mentioned in any document which is making this very hard to do. kindly check this program still this is not working, kindly look into this and and modify it to work.

Thank You

0 Kudos
3,030 Views
vikmonti7804
Contributor III

Hi Lucas,

          There are two apis available to communicate to HSE via host.

hseStatus = Crypto_Hse_SendMsg  from RTD
hseStatus = HSE_Send   from the hse_host.c HSE demo example code

Both has different parameters and the RTD one has too many parameter, can you please suggest which one we should use ?

Also we are developing our code with the help of config tool for compliance with Autosar.

Please reply and also try to resolve the TRNG issue.

0 Kudos
3,023 Views
lukaszadrapa
NXP TechSupport
NXP TechSupport

Hi @vikmonti7804 

I tried to turn off the data cache as a first step:

lukaszadrapa_0-1710765650961.png

And I can see that the random number is generated:

lukaszadrapa_1-1710765661204.png

So, this confirms it's caused by the cache. I can see that you only copied the definitions from the example. But this does not solve the problem. If you take a look at the function:

lukaszadrapa_2-1710765679907.png

... there are local variables used for communication with the HSE via MU and the stack is obviously cacheable because it does not work.

HSE DEMO EXAMPLES is non-autosar code. If you need to be autosar compliant, it will be necessary to use Crypto layer in RTD. You can take a look Crypto examples in RTD - examples with "Crypto_" prefix.

Regards,
Lukas

0 Kudos
2,987 Views
vikmonti7804
Contributor III

Hi Lucas,

       Please find the attached zip file for the firmware , kindly reply me by modifying this fw to generate the random number.

0 Kudos
2,973 Views
lukaszadrapa
NXP TechSupport
NXP TechSupport

I have some troubles to open the project and I can't spend so much time with this. But what I would try:
There are following variables in GetRngNum() used as inputs for HSE: pHseSrvDesc and pGetRndSrv.

To force them to no-cacheable area, you can define them as global variables and use:
#define CRYPTO_43_HSE_START_SEC_VAR_SHARED_CLEARED_UNSPECIFIED_NO_CACHEABLE
See the example in RTD which shows how to do that exactly:

lukaszadrapa_0-1710852711103.png

 

And then do the same for RandomNumber array in main.c file.

Regards,
Lukas

0 Kudos
2,968 Views
vikmonti7804
Contributor III

Hi Lucas,

        what is the problem you are getting to open this project? Please let me know?

I tried in main and rng.c file but still its not working. please share at least the main file after modification if possible

vikmonti7804_0-1710855402478.png

and i tried in rng.c file

vikmonti7804_1-1710855452315.png

 

0 Kudos
3,032 Views
vikmonti7804
Contributor III

Hi Lucas, 

            Kindly help, this RNG is pending from many days and project is lagging behind, kindly help, once its done other things i will take care.

0 Kudos
3,437 Views
vikmonti7804
Contributor III

HI Lucas,

           I am compiling one of the project from RTD package about the crypto but i am facing a issue that while it is going into the debug it goes into the erasing the chip wait for some time and then it suspended due to time out. this is happening with other projects too.

this board was flashed with the HSE FW with linker file.

kindly find the logs of console below

Initializing.
Soft reset failed!
Target has been RESET and is active.
CMD>CM C:\NXP\S32DS.3.5\eclipse\plugins\com.pemicro.debug.gdbjtag.pne_5.1.7.202112141853\win32\gdi\P&E\supportFiles_ARM\NXP\S32K3xx\nxp_s32k312_1x32x500k_hse_disabled.arp

Initializing.
Soft reset failed!
Initialized.

;version 1.00, 08/27/2021, Copyright 2021 P&E Microcomputer Systems, www.pemicro.com [S32K3x2_hse_disabled]

;device nxp, s32k312, 1x32x500k,desc=hse_disabled

;begin_cs device=$00400000, length=$001F4000, ram=$20400000

Loading programming algorithm ...

WARNING - Selected .ARP file has been modified. CRC16 = $ACE3
Done.
Programming sequency is : erase, blank check, program, and verify {default}
CMD>VC
Command is inactive for this .ARP file.
VC is not implemented, falling back to VM

CMD>VM

Verifying.
Verify error at address $00400000.
Byte in module is $FF and should be $A5.
Current content of flash does not match application to be programmed
CMD>EM

Erasing.

Could not connect to semihosting port due to connection timeout. Please check that the correct port number is configured.

0 Kudos
3,433 Views
lukaszadrapa
NXP TechSupport
NXP TechSupport

Once the HSE FW is installed, you need to change flash algorithm because some flash is then reserved for HSE. See please attached screenshot.

Regards,

Lukas

0 Kudos
3,411 Views
vikmonti7804
Contributor III

Hi Lucas , thank you for your support.

i have used the crypto example code for s32k312 from rtd 4.4 2.0.3 and added all the folder services, interface, drivers and framework and trying to use this project for development purpose, but i am stuck in some hardfault and i am not able to resolve.

kindly help and find the attached project.

loges are beow.

Connection from "127.0.0.1" via 127.0.0.1. Connection from port "53301" to 6224
Connection from "127.0.0.1" via 127.0.0.1. Connection from port "53308" to 7224
Telnet server running on 127.0.0.1:51794
Searching for Kernel Symbols...
rsp_qC - qSymbol: 5F74785F7468726561645F63757272656E745F707472
_tx_thread_current_ptr not found. ThreadX analysis not enabled.
rsp_qC - qSymbol: 707843757272656E74544342
pxCurrentTCB not found. FreeRTOS analysis not enabled.
Unable to load libusb0.dll
Copyright 2021 P&E Microcomputer Systems,Inc.
Command Line :C:\NXP\S32DS.3.5\eclipse\plugins\com.pemicro.debug.gdbjtag.pne_5.1.7.202112141853\win32\pegdbserver_console -device=NXP_S32K3xx_S32K312 -startserver -singlesession -serverport=7224 -gdbmiport=6224 -interface=USBMULTILINK -speed=5000 -port=U¨
PEmicro Interface detected - Flash Version 11.13

CMD>RE

Initializing.
Soft reset failed!
Target has been RESET and is active.
CMD>CM C:\NXP\S32DS.3.5\eclipse\plugins\com.pemicro.debug.gdbjtag.pne_5.1.7.202112141853\win32\gdi\P&E\supportFiles_ARM\NXP\S32K3xx\nxp_s32k312_1x32x424k_ab_swap.arp

Initializing.
Soft reset failed!
Initialized.

;version 1.00, 08/27/2021, Copyright 2021 P&E Microcomputer Systems, www.pemicro.com [S32K3x2_ab_swap]

;device nxp, s32k312, 1x32x424k,desc=ab_swap

;begin_cs device=$00400000, length=$001D4000, ram=$20400000

Loading programming algorithm ...

WARNING - Selected .ARP file has been modified. CRC16 = $E7CD
Done.
Programming sequency is : erase, blank check, program, and verify {default}
CMD>VC
Command is inactive for this .ARP file.
VC is not implemented, falling back to VM

CMD>VM

Verifying.
Verified.

Application verified in memory. No need to reprogram.

CMD>RE

Initializing.
Soft reset failed!
Target has been RESET and is active.
Soft reset failed!

Starting reset script (C:\NXP\S32DS.3.5\eclipse\plugins\com.pemicro.debug.gdbjtag.pne_5.1.7.202112141853\win32\gdi\P&E\supportFiles_ARM\NXP\S32K3xx\S32K312.mac) ...
REM Enable clocks for selected cores in MC_ME module (the sequence below enables all clocks).
REM Initialize RAM and DMA:
REM Initialize DMA TCD:
REM Copy valid executable code to RAM for each core to be used.
REM Enable required cores in MC_ME:
Delaying for 20mS ...
Done.

Reset script (C:\NXP\S32DS.3.5\eclipse\plugins\com.pemicro.debug.gdbjtag.pne_5.1.7.202112141853\win32\gdi\P&E\supportFiles_ARM\NXP\S32K3xx\S32K312.mac) completed.

BusFault: An imprecise (asynchronous) data access error has occurred.
HardFault: A fault has been escalated to a hard fault.

0 Kudos
3,398 Views
vikmonti7804
Contributor III

Hi Lucas,

             Before adding these folders services, framework, interface and drivers to the project, the mcal configuration was having no errors but after adding these folders to the projects the mcal configuration is having the errors. please find the attached image. kindly help for hard fault. you can this project i have already attached in previous message.

 If possible provide some time or invite to discuss, can be half an hour call, i need to clarify many things.

vikmonti7804_0-1709788822306.png

 

0 Kudos
3,377 Views
lukaszadrapa
NXP TechSupport
NXP TechSupport

A couple of things:

- the error "Processor..." was caused by missing .settings folder. I added the folder from another project and the problem disappeared.

lukaszadrapa_1-1709819814199.png

- then there were some issues with paths. Not sure why but I fixed it using "workspace" paths like this:

lukaszadrapa_0-1709819805017.png

- and the hard fault was caused by linker file:

lukaszadrapa_2-1709819859074.png

There's only 96KB RAM, so it ends at 0x20417FFF.

Regards,

Lukas

 

0 Kudos
3,370 Views
vikmonti7804
Contributor III
Hi Lucas,           Thanks for the support. But i changed the SRAM configuration in the linker file but the still i see it goes into the hard fault. Did you tried at your end by changing the SRAM values? I changed the configuration with below setting.  MEMORY { int_flash : ORIGIN = 0x00400000, LENGTH = 0x003FFFF /* 2048K - 176K (sBAF + HSE) vikas */ int_itcm : ORIGIN = 0x00000000, LENGTH = 0x00001000 /* 32K */ int_dtcm : ORIGIN = 0x20000000, LENGTH = 0x0001FFFF /* 64K */ int_sram : ORIGIN = 0x20400000, LENGTH = 0x00010000 /* 27 KB */ int_sram_fls_rsv : ORIGIN = 0x20410000, LENGTH = 0x00000100 int_sram_stack_c0 : ORIGIN = 0x20410100, LENGTH = 0x00002000 int_sram_no_cacheable : ORIGIN = 0x20412100, LENGTH = 0x00007F00 /* 32kb , needs to include int_results */ int_sram_results : ORIGIN = 0x2041A000, LENGTH = 0x00000100 int_sram_shareable : ORIGIN = 0x2041A100, LENGTH = 0x00008000 /* 32KB */ ram_rsvd2 : ORIGIN = 0x20422100, LENGTH = 0 /* End of SRAM */ /* End of SRAM */ } kindly check and help to resolve.
0 Kudos