Setting S32K312 PLL then system will reset

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Setting S32K312 PLL then system will reset

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Felix_ar
Contributor III

Hi All,

The customer setting S32K312 PLL then system will reset, attached file is the customer sample code.

could you give me some comments?

thanks.

FUNC(void, SYSDAL_APPL_CODE) SysDal_DriverInitZero(void)

{

    OsIf_Init(NULL_PTR);

    /* Initialise MCU Driver */

#if (MCU_PRECOMPILE_SUPPORT == STD_ON)

    Mcu_Init(NULL_PTR);

#else

    Mcu_Init( &Mcu_Config );

#endif

 

    /* Set the CPU Clock to the PLL */

#if (MCU_INIT_CLOCK == STD_ON)

    Mcu_InitClock(McuClockSettingConfig_HighPerf);  // only do this setting, system will reset every one second. 

#endif

#if(MCU_NO_PLL == STD_OFF)

    /* Wait until the PLL is locked */

    while (MCU_PLL_LOCKED != Mcu_GetPllStatus()); //include this setting, system will reset one time only.

    /* Activate the PLL Clock */

    Mcu_DistributePllClock(); //include this setting, system will reset one time only.

#endif/*MCU_NO_PLL == STD_OFF*/

 

    /* Initialize PORT */

    Port_Init( &Port_Config );

 

    /* Set the MCU to RUN mode */

    Mcu_SetMode(McuModeSettingConf_Run);

 

}

 

Main Loop

    for (;;) {

                (void)Dio_FlipChannel((Dio_ChannelType)DioConf_DioChannel_View1);

    }

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1 Solution
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Robin_Shen
NXP TechSupport
NXP TechSupport

Hi

Please check if it is related to the reasons mentioned in the following discussion:
If I don't give s32k312 delay, the CAN stop during operation

I checked your Clock_Ip_PBcfg.c, and it seems to be caused by it:

{
AIPS_SLOW_CLK,
4U,
{
0U,
}
},

{
HSE_CLK,
1U,
{
0U,
}
},


Best Regards,
Robin
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Felix_ar
Contributor III

Hi Robin

Thank for your reply, the system reset problem is fixed.

One more question, S32K3xx_DCF_clients.xlxs mentions HSE_CLK_MODE_AND_GSKT_CTRL register can set to 1x then HSE clock can set up to 120MHz, but how to change register setting?

Because I can't find HSE_CLK_MODE_AND_GSKT_CTRL register in reference manual, I have found related register is HSE_CLK_MODE_OPTION, but that is read only register.

Thanks.

HSE_CLK.png

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Robin_Shen
NXP TechSupport
NXP TechSupport

Please refer to the discussion in HSE PLL configuration.

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263 Views
Robin_Shen
NXP TechSupport
NXP TechSupport

Hi

Please check if it is related to the reasons mentioned in the following discussion:
If I don't give s32k312 delay, the CAN stop during operation

I checked your Clock_Ip_PBcfg.c, and it seems to be caused by it:

{
AIPS_SLOW_CLK,
4U,
{
0U,
}
},

{
HSE_CLK,
1U,
{
0U,
}
},


Best Regards,
Robin
-------------------------------------------------------------------------------
Note:
- If this post answers your question, please click the "Mark Correct" button. Thank you!

- We are following threads for 7 weeks after the last post, later replies are ignored
Please open a new thread and refer to the closed one, if you have a related question at a later point in time.
-------------------------------------------------------------------------------

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