SM1.FLASH.AI_SELFCHECK and MEM_43_INFLS/C40_Ip RTD

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SM1.FLASH.AI_SELFCHECK and MEM_43_INFLS/C40_Ip RTD

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FabioG
Contributor III

Hi There.

We are implement SM1.FLASH.AI_SELFCHECK safety mechanism using MEM_43_INFLS and the C40_Ip rtd. Is this the righe way to implement it?. I 'd ask you if there is an axample code available.

We have 2 problems:

1.-The Array integrity check goes in HardFault (Instruction bus error). Seems that the functions for the AI must be allocated in a RAM section. How we can configurate the modules Mem_43_INFLS and C40_Ip to allocate the functions in RAM? 

 

2.- How we can calculate the MISR of the Flash offline?. I am reading the manuals and the calculation of the MISR of our binary is not clear, I supose a tool must be downloaded, but is not clear.

Thanks

 

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Julián_AragónM
NXP TechSupport
NXP TechSupport

Hi @FabioG,

1. You can refer to the following post on how to move the API function to the RAM section: Solved: S32K344 C40 IP Hardware Fault Problem - NXP Community

2. Currently, there is no tool available for the S32K family. There are some old examples and tools (such as the following community posts: Example MPC5744P FlashArrayIntegrityCheck test SSD GHS614 - NXP Community, Solved: What is MISR and how to calculate MISR? - NXP Community. These tools are not fully compatible with the S32K3 devices since configuration parameters do not match with the S32K3 flash layout. 

The way to calculate the expected MISR values is by using the Integrity Check driver itself. The MISR should be calculated with "gold samples" approach - so use some samples for calculation and use it.

MISR values are like a CRC, and these values are dependent on the data stored in memory, and not on the device, if you run the same test in a sample under the same values and the same memory contents, you should get the same result.

Chapter 21.5.4.1 (Array integrity self-check) from the reference manual explains the array integrity self-check steps.

Best regards,
Julián

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FabioG
Contributor III

Hi @Julián_AragónM

Thanks you for informations.

In order to implement SM1.FLASH.SELFCHECK for s32k344  ASILD, the MISR should  be calculated by an external tool, and in production we  will need to change EOL with this feature; so  we need, at least, the agorithm  for MISR calculation, suitable for S32k344 in order to build our own external tool. (MISR_Cxx.exe). Is it possible? 

Best regards,

Fabio

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Julián_AragónM
NXP TechSupport
NXP TechSupport

Hi @FabioG,

An Array Integrity Check is calculated on top of the Flash content from the customer. As such the corresponding value is dependent on the programming of this content. 

This is why calculating it during development with the hardware is a better approach, as sometimes it is difficult to get the same results from the parameters (ensuring a proper padding to the programming page boundaries, srecord file, etc.)

Best regards,
Julián

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Julián_AragónM
NXP TechSupport
NXP TechSupport

Hi @FabioG,

1. You can refer to the following post on how to move the API function to the RAM section: Solved: S32K344 C40 IP Hardware Fault Problem - NXP Community

2. Currently, there is no tool available for the S32K family. There are some old examples and tools (such as the following community posts: Example MPC5744P FlashArrayIntegrityCheck test SSD GHS614 - NXP Community, Solved: What is MISR and how to calculate MISR? - NXP Community. These tools are not fully compatible with the S32K3 devices since configuration parameters do not match with the S32K3 flash layout. 

The way to calculate the expected MISR values is by using the Integrity Check driver itself. The MISR should be calculated with "gold samples" approach - so use some samples for calculation and use it.

MISR values are like a CRC, and these values are dependent on the data stored in memory, and not on the device, if you run the same test in a sample under the same values and the same memory contents, you should get the same result.

Chapter 21.5.4.1 (Array integrity self-check) from the reference manual explains the array integrity self-check steps.

Best regards,
Julián

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