S32K358 SPI3 Communication abnormal when core clock is greater than 160M

[yongs]

question:

S32K358, use RTD 4_4_2,  When the CORE CLOCK is greater than 160M (240M verified) SPI3 communication is abnormal; when the core clock is less than 160M SPI3 communication is normal.

[VaneB]

Hi @yongs 

The configuration of the CORE_CLK to a frequency of 240 MHz corresponds to Option A+ (High-Performance mode) of the system clocking configuration. To be able to enable Option B/A+(S32K358)/ A++(S32K388) is stated that the "host application must program the UTEST Miscellaneous register (UTEST_MISC): dcf_client_utest and must configure the HSE_CLK_MODE_AND_GSKT_CTRL (bit 30-29) in this register."

For more details, refer to the DCF Clients file in the Device Reference Manual and the HSE_B Firmware Reference Manual.

B.R

VaneB