Hi @Xjh193,
If TXMSK = 0, a new transfer is initiated only when the Transmit Data Register is written, so, if there is only one 32bit write to the FIFO, the module should send just one 32bit frame (FRAMESZ = 31).
Do you need to reset the FIFOs in the function?
There is an erratum regarding the FIFO reset:
ERR050456: LPSPI: Reset to fifo does not work as expected
https://www.nxp.com/webapp/Download?colCode=S32K3X4-0P55A-1P55A-ERRATA
Can you please try without the two writes to the Control Register?
Regards,
Daniel
hi @Daniel, the bug cause we found slow clock is not configured by MCU_CGM register.
Thank you!