S32K312 - SPI Clock, MOSI make wrong pulse

[ssean]

Hello.

When I send data to MOSI by called Spi_SyncTansmit(), SCK and MOSI make wrong pulse at start.

It happen only in use CPOL=1(Clock Idle HIGH, Active LOW).

If I set CPOL=0 (Clock Idle Low, Active HIGH), it is okay.

* RTD Version 2.0.1 (7, July, 2022)

1. Send 0x00 00

 

2. Send 0x07 31

3. LPSPI_1 Register value

Best Regards,

Sean Sung

[danielmartynek]

Hi @ssean,

It was discussed here:

https://community.nxp.com/t5/S32K/S32K3-SPI-CS-problem-when-using-GPIO-to-simulate-CS/td-p/1564367

The module is reset at the beginning of each transfer.

Normally, with your configuration OUTCFG = 0, the MOSI line should retains last value when chip select is negated (beetween transfers).

But the module is reset in the driver.

Regards,

Daniel

[ssean]

Dear @danielmartynek 

Thank you for reply.

It happen with OUTCFG=1, too.

Can you give me advise for how can I fix this problem?

Best Regards,

SEAN SUNG

[danielmartynek · Accepted solution]

Dear @ssean,

The issue is that the Lpspi_Ip_SyncTransmit() resets the LPSPI module in function Lpspi_TransmitTxInit().

You would need to remove the code that reset the LPSPI from the function.

Regards,

Daniel

[ssean]

Dear @danielmartynek 

I fix this issue to CS control by peripheral engine (not GPIO).

Thank you for reply.