S32K3

[Zhiwei]

When testing the MCAL DMA scatter-gather function , I found the following problems, I hope you can help answer the doubts:

①Disable the D-Cache and I-Cache, the DMA transfer result is correct, and can enter the interrupt normally;

②Enable D-Cache and I-Cache, DMA can not complete the transfer, only transfer completed ELEMENT_0, check the TCD0_DLAST_SGA register and find that the address is 0x00;

The RTD version tested is RTD2110, and the IP routine test DMA scatter-gather function did not find this problem. The attachment is a test routine. If your company can provide the MCAL routine of DMA scatter-gather, I would be very grateful. Then I can try to compare and find the error.

Thank you so much!

[frank_yang_1_offboarding]

     The user should deassert compile option "Data sections(-fdata-sections)" in project properties for making macro MCL_START_SEC_VAR_CLEARED_UNSPECIFIED_NO_CACHEABLE valid.

               

      If the user needs place functions to specific section, the option compile option "Function sections(-ffunction-sections)" will be also should be deassert.

      If the user deassert these options, the rough method which shown above(__attribute__((section(".mcal_bss_no_cacheable"))) is not necessary anymore.

[frank_yang_1_offboarding]

The cache make the DMA engine load the next TCD from cache instead of its actual address.

There is an initial rough method to solve this problem:

• Locate the the generated file Dma_Ip_PBcfg.c in path .\Generated\src.
• Find the Dma_Ip_SwTcdRegType structural parameters. It is the external software TCD elements which would be loaded into DMA.
• Specify its link property and assign it into section mcal_bss_no_cacheable. (e.g. __attribute__((section(".mcal_bss_no_cacheable")))) 

                         

   The user should note that this additional property will be removed when user generate project in EB.

   The attachment is the modified project based on the provided.

[Zhiwei]

@frank_yang_1_offboarding Thank you for your reply!

The solution you provided is ok, but there are still the following doubts(Personal understanding, if wrong please correct

① As shown in the figure, with "MCL_START_SEC_VAR_CLEARED_UNSPECIFIED_NO_CACHEABLE", the structure variables should be stored in the nocache area, but they are not.

(2) The DMA controller loads the software TCD into the TCD register, which should not use DMA handling. There is no inconsistency between cache line data and physical address data.

[frank_yang_1_offboarding · Accepted solution]

     The user should deassert compile option "Data sections(-fdata-sections)" in project properties for making macro MCL_START_SEC_VAR_CLEARED_UNSPECIFIED_NO_CACHEABLE valid.

           

      If the user needs place functions to specific section, the option compile option "Function sections(-ffunction-sections)" will be also should be deassert.

      If the user deassert these options, the rough method which shown above(__attribute__((section(".mcal_bss_no_cacheable"))) is not necessary anymore.

[Zhiwei]

Thank you very much! I got it!