S32K148 SPI+DMA ISSUE

[zhouxiang1]

When I use spi+dma as master to transmit 6 bytes, CS is controlled by GPIO, the TX interrupt happens at the end of the forth byte, but not at the end of the last byte. (set CS to HIGH in the TX interrupt) What can I do? Thanks!

[zhouxiang1]

I solve it. CS is controlled by GPIO, spi transfer is controlled by dma, deactive CS in the LPSPI interrupt (Transfer Complete Interrupt), but not in the dma interrupt.

[danielmartynek · Accepted solution]

Hello @zhouxiang1,

By the TX interrupt, I understand this is an interrupt at the end of the DMA transfer.

The DMA transfer completes as soon as the data are transfered to the LPSPI TX FIFO not at the end of the LPSPI transfer.

Why do you need a GPIO CS? The LPSPI module support continuous transfer mode that keeps the CS asserted between frames.

Regards,

Daniel

[zhouxiang1]

In some situation, CS need to sync with some other signals. For example, active CS first, and wait a postedge on some GPIO, then start SPI transmition. Could I implement this kind of requirement with hardware CS? 

[danielmartynek]

Do you mean Host Request?

Thanks,

BR, Daniel

[zhouxiang1]

Thanks for your suggestion about TRGMUX, I will read the chapter later. Are there some configurations what I can do to enable a interrupt at the end of LPSPI transfer?