S32K144 multiple interrupt enable

[PradeepAithal]

I am trying to enable multiple interrupts one after the other, but only one interrupt which is enabled first is activated.

Please find below the snippet of the code (in this case only LPIT0 is interrupt is generated)

void NVIC_IRQs_Init (void)

{

  S32_NVIC->ICPR[1] = 1 << (48 % 32);  /* IRQ48-LPIT0 ch0: clr any pending IRQ*/

  S32_NVIC->ISER[1] = 1 << (48 % 32);  /* IRQ48-LPIT0 ch0: enable IRQ */

  S32_NVIC->IP[48] = 0x3;             /* IRQ48-LPIT0 ch0: priority 0 of 0-15*/

  S32_NVIC->ICPR[1] |= (1 << (33 % 32));  /* IRQ33-LPUART ch1: clr any pending IRQ*/

  S32_NVIC->ISER[1] |= (1 << (33 % 32));  /* IRQ33-LPUART ch1: enable IRQ */

  S32_NVIC->IP[33] = 0x1;             /* IRQ33-LPUART ch1: priority 2 of 0-15*/

}

void LPIT0_Ch0_IRQHandler (void)

{

  LPIT0->MSR |= LPIT_MSR_TIF0_MASK; /* Clear LPIT0 timer flag 0 */

          /* Perform read-after-write to ensure flag clears before ISR exit */

}

void LPUART1_RxTx_IRQHandler (void)

{

       char receive;

       if(LPUART1->STAT & LPUART_STAT_RDRF_MASK)

              {

              receive= LPUART1->DATA;            /* Read received data*/

              }

       while((LPUART1->STAT & LPUART_STAT_TDRE_MASK)>>LPUART_STAT_TDRE_SHIFT==0);

}

If i initialize UART interrupt only, then UART interrupt will be activated.

PN: Designed with the help of S32K cookbook

[chicheportichen]

Thank you for the answer Daniel.

That wasn't also clear to me.

Referring to the Handbook : 

         FSL_NVIC->IP[48] =0x0A; /* IRQ48-LPIT0 ch0: priority 10 of 0-15*/

==> The priority level actually here is 2 not 10.

Is mu understanding correct ?

BR,

nicolas

[danielmartynek]

Hello Nicolas. 

The priority number would be 0 in this case.

If you want to set priority number 2, it would be:

S32_NVIC->IP[48] = 0x20; (0b00100000)

BR, Daniel

[danielmartynek]

Hello pradeep.aithal@in.bosch.com,

The NVIC_IRQs_Init() function only clear the NVIC pending flags of the two interrupts and enables them, it seems to be correct, but there is no need to use the read-modify-write operation.

Is it possible that the application is in the LPIT ISR the whole time? 

Because the priorities are not set correctly.

The number must be written to the 4 MSB of the IP registers. 

So, your configuration sets the priorities of the two interrupts to 0 (highest).

If you expect the UART interrupt to preempt the LPIT interrupt, this won't work. 

Can you share the project?

BR, Daniel

[PradeepAithal]

Dear Daniel,

Thanks for your support.

Please find attached

Best regards,

Pradeep Aithal

RBEI/EMS

Tel. +91 80 6136-3754

[danielmartynek]

Dear Pradeep Aithal,

I have just tested the example, the NVIC module is set correctly except for the IP priority registers.

I understand you want to trigger the LPUART1 receive interrupt but it is not enabled in the LPUART1 module:

BR, Daniel