S32K144 FTM PWM HICCUP(Frequent enable and disadle)

cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 

S32K144 FTM PWM HICCUP(Frequent enable and disadle)

719 Views
WEIFAN
Contributor I

I use FTM to configure PWM combined.

When the PWM module controls burping, the duty cycle of the first wave on and the last wave off is random. Two PWM circuits do not switch simultaneously.

 

waveform:

WEIFAN_1-1687848107522.png

WEIFAN_2-1687848146296.png

 

 

Hiccup control:

if(flag == 1)        //“flag” changes before 0 and 1
{
      FTM0->SC &= 0xFF0FFFF; //disable pwm ch 0123
}
else
{
     FTM0->SC |= 0x00F0000; //enable pwm ch0123

}

FTM0->SYNC |= 0x80;

PWM configuration:

WEIFAN_0-1687847486454.png

I want both PWM circuits to switch on and off simultaneously with the same duty cycle。thanks。

Tags (1)
0 Kudos
3 Replies

701 Views
Robin_Shen
NXP TechSupport
NXP TechSupport

Hi WEIFAN,

Sorry, can you tell me what or what is the relationship between C1 and C4?
C1 and C4 seems not in Complementary mode, otherwise the channel (n+1) output should be the inverse of the channel (n) output.

47.5.11 Complementary Mode.jpg

Seems that you are using FTM_SC[PWMENn] control the value of channel output. But it will disable or enable the output immediately after you write to the register, it will not wait for FTM_CNT=CNTIN to change the output. 47.5.33 External Control of Channels Output.jpg

Sorry I may not understand what kind of PWM waveform you expect to generate? Is it convenient to draw your desired waveform on the oscilloscope waveform graph?

Have a look at 47.5.15 Software Output Control Mode, do the channel (n) and channel (n+1) output after the software output control shown in Figure 47-74 is the waveform what you want?

47.5.15 Software Output Control Mode.jpg
Best Regards,
Robin

0 Kudos

685 Views
WEIFAN
Contributor I

Hi,

I am very happy to receive your reply.

Sorry, I didn't find the waveform I needed。

WEIFAN_0-1688040333014.png

 
 

As shown in the above figure,CH1-CH4 is enable or disable at the rising or falling edge to ensure complete duty cycle。

Figure 2,I drew a waveform myself。

WEIFAN_1-1688042355273.png
                           Figure 2
 
 CH0-CH4 PWM Combined configaration
WEIFAN_2-1688042606460.png

 

 

Best Regards,
WeiFan

 

Tags (1)
0 Kudos

630 Views
Robin_Shen
NXP TechSupport
NXP TechSupport

Because channel 0\1\2\3 must output low level voltage after DISABLE, I think you can consider using 47.5.15 Software Output Control Mode. But you need to pay attention to: select enhanced PWM synchronization (SWOC = 1 and SYNCMODE = 1) in 47.5.13.9 SWOCTRL register synchronization. And write SWSYNC (47.5.13.2 Software trigger) in the FTM interrupt to realize the software output control at the selected 47.5.13.3 Synchronization Points. Additionally you need to make sure SWRSTCNT=0 to avoid resetting the FTM counter when writing SWSYNC to software trigger.

0 Kudos