S32K118 go to HardFault when in non-privileged mode accessing the PTA register

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S32K118 go to HardFault when in non-privileged mode accessing the PTA register

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LijieDu
Contributor II

LijieDu_0-1677066058416.png

It says it is accessible for both privileged
and unprivileged code when access Peripheral

But when I change the Control register with the following assembly code:

/* void ResetPrivileged( void ) */

ResetPrivileged:

MRS r0, control 
MOVS r1, #1
ORRS r0, r0, r1 
MSR control, r0 
DSB
ISB
BX lr

and access the register PTA->PSOR = (1ul << 5) 

it go to the HardFault Handler

So in the non-privileged mode, can I access the registers of peripheral devices?

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danielmartynek
NXP TechSupport
NXP TechSupport

Hi @LijieDu,

Sorry, I meant OPACRF.

 

OPACRA[SP0] is FTFC

OPACRA[SP1] is DMAMUX

...

OPACRF[SP1] is PortA

 

BR, Daniel

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danielmartynek
NXP TechSupport
NXP TechSupport

Hi @LijieDu,

It is protected by the AIPS.

Have a look at Peripheral Memory Map in the S32K1xx_Memory_Map.xlsx file that is attched to the RM.

PortA is configurable in PACRF[26-24].

You would need to clear OPACRF[26].

 

Regards,

Daniel

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LijieDu
Contributor II

First of all, thank you for your answer

PACRF register not found in the reference manual Rev13 below:

 

LijieDu_0-1677418262717.png

I can't understand the memory mapping table. Can you explain how to map one to one in detail

LijieDu_1-1677418371300.png

 

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danielmartynek
NXP TechSupport
NXP TechSupport

Hi @LijieDu,

Sorry, I meant OPACRF.

 

OPACRA[SP0] is FTFC

OPACRA[SP1] is DMAMUX

...

OPACRF[SP1] is PortA

 

BR, Daniel

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LijieDu
Contributor II

hi @danielmartynek 

Thanks for your reply

Sorry, maybe I didn't describe the problem correctly,PTA type is GPIO_Type defined in s32k118.h

LijieDu_0-1677552106794.png

According to your prompt,and Refer to map table below, I clear the bit 3 of PACRB and can control IO output in user mode,it did not go to hardfault again

LijieDu_1-1677552386146.png

Thanks very much!

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