Rise time and fall time requirement for S32K3 LPSPI Clock

[Shanjai]

Hi, 

I am shanjai kanna from HCL. We are simulating SPI interface of S32K342NHT0MPBSR with another SoC FPGA. Here, SoC FPGA act as master and NXP S32K3 act as slave. While checking rise time and fall time for SPI Clock, they are greater than NXP S32K3 requirement (i.e.1ns). I am attaching NXP S32K3 rise time/fall time requirement in below image. We are getting 1.697ns rise time and 1.364ns fall time. Is it okay to get 0.697ns rise time and 0.364ns fall time more than NXP S32K3 requirement? 

Thanks,

Shanjai kanna S

[danielmartynek]

Hi @Shanjai,

The Rise/Fall time is measured with respect to 20% VDD_HV_A/B and 80% VDD_HV_A/B thresholds.

How do you measure the slew rate in your setup?

The 1ns specification simply says that the LPSPI has been validated at 1ns input signal - at slower rise/fall time, NXP does not guarantee the other LPSPI specifications.

It means the LPSPI does not require a specific rise/fall time as long as the other specifications are met (input setup, input hold, valid output, etc).

Regards,

Daniel

[Shanjai]

Hi @danielmartynek , We also measured with respect to 20% VDD_HV_A/B and 80% VDD_HV_A/B thresholds. We done timing analysis (Setup time and hold time) for LPSPI and met with input setup time and input hold time specifications. Is it okay?

Thanks,

Shanjai kanna S

[danielmartynek]

Hi @Shanjai,

We don't have the LPSPI validated at a different input signal.

It is the user responsibility to ensure all the other requirements are met at a different input signal.

The input slew rate gets more important at higher baudrates.

Regards,

Daniel