Regarding MRC in S32K3

[FXY]

There is an MRC in the Resource Domain Control Module (XRDC), 

I would like to know the difference in purpose or characteristics between MRC, MPU, and MMU?And the advantages and disadvantages？

[danielmartynek]

Hello @FXY,

The S32K3xx CM7 cores have each an MPU which allows isolation of tasks that run on that core.

The XRDC is basically a system-level MPU (MRC at least) which sits at the crossbar switch (AXBS), and it allows isolation of the idividual masters (cores, DMA, ...) and the slaves on the bus (both memories and peripherals).

RM, Figure 8. Block diagram – S32K324, S32K344 and S32K314

There is no MMU:

There is a good training on the S32G XRDC that is similar to the S32K3 one:

https://www.nxp.com/design/training/understanding-the-s32g-extended-resource-domain-controller-xrdc:...

Regards,

Daniel

[FXY]

Hello  Daniel,

1. Assume that we classify the software components into different COREs of S32K3 by ASIL level, with one soft watchdog per CORE. Can the soft watchdog reset only CORE1 and keep CORE2 running when the APP in CORE1 fails? Do we need to use XRDC to implement it?

2. Assume that within a CORE of S32K3, we use MPU tools to rank software components into ASIL levels. Which architecture within S32K will result in the above design scheme not meeting the independent requirements of functional security?

3. Assuming that we have three software components of different security levels, QM, ASILB, ASILD, how many COREs of S32K are recommended?

[danielmartynek]

Hello @FXY,

The SWT reset can be demoted to an interrupt.

Functional safety is out of the scope of this community.

Please refer to the Safety manual.

Or post your questions on the SafeAssure NDA community:

https://community.nxp.com/t5/SafeAssure-NDA-group/gh-p/52177

SafeAssure Program:

https://www.nxp.com/applications/enabling-technologies/functional-safety/safeassure-program:SAFETYPR...

Regards,

Daniel