Lauch debug failed, why ERROR: Failed to measure CPU clock frequency and how to fix?

[qinxk]

MCU：S32K144

Console log:

SEGGER J-Link GDB Server V7.00a Command Line Version

JLinkARM.dll V7.00a (DLL compiled Apr 16 2021 15:32:47)

Command line: -if swd -device S32K144 -endian little -speed auto -port 2331 -swoport 2332 -telnetport 2333 -vd -ir -localhostonly 1 -singlerun -strict -timeout 0 -nogui
-----GDB Server start settings-----
GDBInit file: none
GDB Server Listening port: 2331
SWO raw output listening port: 2332
Terminal I/O port: 2333
Accept remote connection: localhost only
Generate logfile: off
Verify download: on
Init regs on start: on
Silent mode: off
Single run mode: on
Target connection timeout: 0 ms
------J-Link related settings------
J-Link Host interface: USB
J-Link script: none
J-Link settings file: none
------Target related settings------
Target device: S32K144
Target interface: SWD
Target interface speed: auto
Target endian: little

Connecting to J-Link...
J-Link is connected.
Firmware: J-Link V9 compiled Dec 13 2022 11:14:50
Hardware: V9.70
S/N: 69730333
Feature(s): RDI, GDB, FlashDL, FlashBP, JFlash
Checking target voltage...
Target voltage: 3.32 V
Listening on TCP/IP port 2331
Connecting to target...
Connected to target
Waiting for GDB connection...Connected to 127.0.0.1
Reading all registers
Read 4 bytes @ address 0x00000000 (Data = 0x20007000)
Received monitor command: speed 4000
Target interface speed set to 4000 kHz
Received monitor command: clrbp
Received monitor command: reset
Resetting target
Received monitor command: halt
Halting target CPU...
...Target halted (PC = 0x00000420)
Received monitor command: regs
R0 = 00000000, R1 = 00000000, R2 = 00000000, R3 = 00000000
R4 = 00000000, R5 = 00000000, R6 = 00000000, R7 = 00000000
R8 = 00000000, R9 = 00000000, R10= 00000000, R11= 00000000
R12= 00000000, R13= 20007000, MSP= 20007000, PSP= 00000000
R14(LR) = FFFFFFFF, R15(PC) = 00000420
XPSR 01000000, APSR 00000000, EPSR 01000000, IPSR 00000000
CFBP 00000000, CONTROL 00, FAULTMASK 00, BASEPRI 00, PRIMASK 00

Security extension regs:
MSP_S = 00000000, MSPLIM_S = 00000000
PSP_S = 00000000, PSPLIM_S = 00000000
MSP_NS = 20007000, MSPLIM_NS = 00000000
PSP_NS = 00000000, PSPLIM_NS = 00000000
CONTROL_S 00, FAULTMASK_S 00, BASEPRI_S 00, PRIMASK_S 00
CONTROL_NS 00, FAULTMASK_NS 00, BASEPRI_NS 00, PRIMASK_NS 00

Reading all registers
Read 4 bytes @ address 0x00000420 (Data = 0x490BB672)
Received monitor command: speed auto
Select auto target interface speed (2000 kHz)
Received monitor command: flash breakpoints 1
Flash breakpoints enabled
Received monitor command: semihosting enable
Semi-hosting enabled (Handle on BKPT)
Received monitor command: semihosting IOClient 1
Semihosting I/O set to TELNET Client
Received monitor command: SWO DisableTarget 0xFFFFFFFF
SWO disabled successfully.
Received monitor command: SWO EnableTarget 0 0 0x1 0
ERROR: Failed to measure CPU clock frequency: second loop count is less than first one! (0<=12880)

Failed to enable SWO. Could not measure target CPU frequency.
Read 4 bytes @ address 0x00000420 (Data = 0x490BB672)
Read 2 bytes @ address 0x00000410 (Data = 0x0102)
Read 2 bytes @ address 0x00000412 (Data = 0x0002)
Read 2 bytes @ address 0x00000414 (Data = 0xFFFF)
Read 2 bytes @ address 0x00000416 (Data = 0xFFFF)
Read 2 bytes @ address 0x00000418 (Data = 0xFFFF)
Read 2 bytes @ address 0x0000041A (Data = 0xFFFF)
Read 2 bytes @ address 0x0000041C (Data = 0xFFFF)
Read 2 bytes @ address 0x0000041E (Data = 0xFFFF)
Downloading 1024 bytes @ address 0x00000000 - Verified OK
Downloading 16 bytes @ address 0x00000400 - Verified OK
Downloading 4096 bytes @ address 0x00000410 - Verified OK
Downloading 4096 bytes @ address 0x00001410 - Verified OK
Downloading 4096 bytes @ address 0x00002410 - Verified OK
Downloading 4096 bytes @ address 0x00003410 - Verified OK
Downloading 4096 bytes @ address 0x00004410 - Verified OK
Downloading 4096 bytes @ address 0x00005410 - Verified OK
Downloading 4096 bytes @ address 0x00006410 - Verified OK
Downloading 4096 bytes @ address 0x00007410 - Verified OK
Downloading 4096 bytes @ address 0x00008410 - Verified OK
Downloading 4096 bytes @ address 0x00009410 - Verified OK
Downloading 4096 bytes @ address 0x0000A410 - Verified OK
Downloading 4096 bytes @ address 0x0000B410 - Verified OK
Downloading 4096 bytes @ address 0x0000C410 - Verified OK
Downloading 4096 bytes @ address 0x0000D410 - Verified OK
Downloading 4096 bytes @ address 0x0000E410 - Verified OK
Downloading 4096 bytes @ address 0x0000F410 - Verified OK
Downloading 4096 bytes @ address 0x00010410 - Verified OK
Downloading 4096 bytes @ address 0x00011410 - Verified OK
Downloading 4096 bytes @ address 0x00012410 - Verified OK
Downloading 4096 bytes @ address 0x00013410 - Verified OK
Downloading 4096 bytes @ address 0x00014410 - Verified OK
Downloading 4096 bytes @ address 0x00015410 - Verified OK
Downloading 4096 bytes @ address 0x00016410 - Verified OK
Downloading 4096 bytes @ address 0x00017410 - Verified OK
Downloading 4096 bytes @ address 0x00018410 - Verified OK
Downloading 4096 bytes @ address 0x00019410 - Verified OK
Downloading 4096 bytes @ address 0x0001A410 - Verified OK
Downloading 4096 bytes @ address 0x0001B410 - Verified OK
Downloading 4096 bytes @ address 0x0001C410 - Verified OK
Downloading 4096 bytes @ address 0x0001D410 - Verified OK
Downloading 2560 bytes @ address 0x0001E410 - Verified OK
Downloading 8 bytes @ address 0x0001EE10 - Verified OK
Downloading 504 bytes @ address 0x0001EE18 - Verified OK
Downloading 92 bytes @ address 0x0001F010 - Verified OK
ERROR: Timeout while preparing target, RAMCode did not respond in time. (PC = 0x00000000, CPSR = 0x00000000, LR = 0x41000000)!
Failed to prepare RAMCode using RAM
Writing register (PC = 0x 410)
WARNING: Failed to read memory @ address 0x00000410
Received monitor command: clrbp
Received monitor command: reset
Resetting target
Received monitor command: halt
Halting target CPU...
...Target halted (PC = 0x00000420)
Read 2 bytes @ address 0x00001908 (Data = 0x79FB)
Read 2 bytes @ address 0x00001908 (Data = 0x79FB)
Read 2 bytes @ address 0x00001908 (Data = 0x79FB)
Received monitor command: regs
R0 = 00000000, R1 = 00000000, R2 = 00000000, R3 = 00000000
R4 = 00000000, R5 = 00000000, R6 = 00000000, R7 = 00000000
R8 = 00000000, R9 = 00000000, R10= 00000000, R11= 00000000
R12= 00000000, R13= 20007000, MSP= 20007000, PSP= 00000000
R14(LR) = FFFFFFFF, R15(PC) = 00000420
XPSR 01000000, APSR 00000000, EPSR 01000000, IPSR 00000000
CFBP 00000000, CONTROL 00, FAULTMASK 00, BASEPRI 00, PRIMASK 00

Security extension regs:
MSP_S = 00000000, MSPLIM_S = 00000000
PSP_S = 00000000, PSPLIM_S = 00000000
MSP_NS = 20007000, MSPLIM_NS = 00000000
PSP_NS = 00000000, PSPLIM_NS = 00000000
CONTROL_S 00, FAULTMASK_S 00, BASEPRI_S 00, PRIMASK_S 00
CONTROL_NS 00, FAULTMASK_NS 00, BASEPRI_NS 00, PRIMASK_NS 00

Reading all registers
Read 4 bytes @ address 0x00000420 (Data = 0x490BB672)
Read 2 bytes @ address 0x00000410 (Data = 0x0102)
Read 2 bytes @ address 0x00000412 (Data = 0x0002)
Read 2 bytes @ address 0x00000414 (Data = 0xFFFF)
Read 2 bytes @ address 0x00000416 (Data = 0xFFFF)
Read 2 bytes @ address 0x00000418 (Data = 0xFFFF)
Read 2 bytes @ address 0x0000041A (Data = 0xFFFF)
Read 2 bytes @ address 0x0000041C (Data = 0xFFFF)
Read 2 bytes @ address 0x0000041E (Data = 0xFFFF)
Setting breakpoint @ address 0x00001908, Size = 2, BPHandle = 0x0001
Starting target CPU...

[VaneB]

Hi @qinxk 

This issue could be caused due to some conflict between versions of Segger J-Link SW. It could be the newer install overwrote the old one or maybe just some shared files and broke the older SW.

Try if the following works for you:

• Uninstall the new SW and see if the debugger works again.
• Install S32 Design Studio again, to a new folder location (you can install it multiple times, just gets hard to manage which one to use) and check if the new install works.

Additionally, this problem has been discussed in other posts. Check them it might be useful for you. 

S32K116

Unable to debug using ‘S32 Design Studio for Arm’ and Segger J-Link Classic Base

If the problem persists, contact Segger about this. It is their SW.

B.R.

VaneB