Issue when using LPSPI and TDBR data burst register with DMA

[R20220311]

We have the following concept we would like to implement S32K3xx
We have SyncTransmit code working using the RTD2.0.0 code but would like to switch to DMA transfers. 

Concept:
Use the PIT to periodically transfer 6x16 bit of data on the LPSPI0 module.
We use 16 bit transfers on the SPI bus with a chip select toggle in between to communicate with an ADS7950 ADC. 
The RX side then receives the data based on the RXFIFO being full using the RX fifo flags and DMA. 

I configured the transfer using some copy pasting of RTD2.0.0 Lpspi code see attachment dma_spi_burst_example.zip Note that this example code uses a software trigger for the time being. 

I configured the TCR register for 16 bit transfers on the SPI bus and afterwards.
I let the DMA transfer write into the TDBR register (burst data) on entry TDBR[0] .... TDBR[15].
I masked the RXdata to debug the TX transfers. 

As a test I try to transfer this array on the SPI bus
uint16_t lpspi_tx_data[16] = {0x1010, 0x1111, 0x2222, 0x3333,
0x4444, 0x5555, 0x6666, 0x7777,
0x8888, 0x9999, 0xAAAA, 0xBBBB,
0xCCCC, 0xDDDD, 0xEEEE, 0xBEEF};

Issue: 
After writing the TCR and writing to the TDBR[0] .... TDBR[15] using DMA.
I only see element 0 up to 4 on the SPI bus and afterwards element 15. 
see attachment logic_analyzer_output_spi_transfer.png

Main Question:
-1- So I'm wondering how I can use the TDBR memory map to properly write more then 5 elements on the SPI bus using DMA without the need to use the TX fifo empty flag. 

Other Questions:
-a- Do you have some example of using the TDBR to do multiple transfers on the SPI bus
-b- Can you clarify in a diagram what the relation is between the TDBR the TDR and the internal FIFO and how the S32K3xx keeps track of which element of the TDBR has been written on the SPI bus. 
(The reference manual is a bit lacking on this point)

Thanks in advance, 

Regards Rob van de Voort

[R20220311 · Accepted solution]

@DanNguyenDuyfrom another discussion I found that the Burst registers also write to the fifo in the same way as the normal TDR / RDR registers.
So we still need to split up the DMA transfer in multiple transfers.

The benefit of the Burst register would be that you can write the command (TCBR) and data registers in one single DMA transfer.
Because of this we are just using the TDR and RDR registers and will skip investigating the burst registers.
Thanks for your fast response to this issue.

Explanation of burst registers can be found here:
https://community.nxp.com/t5/S32K/LPSPI-burst-interface/m-p/1483313/emcs_t/S2h8ZW1haWx8dG9waWNfc3Vic...

[R20220311]

Attached the visualization of the configuration I now use.

[R20220311]

We also solved the periodic triggering.
DMAMUX allows for channels 1, 2, 3, 4 to be triggered by PIT0 CHx (x being the DMA channel)
DMA channel 1 -> PIT 0 CH1
DMA channel 2 -> PIT 0 CH2
etc.

By setting the CHCFGx[TRIG] = 0x1 in the DMAMUX (or by selecting Trigger enbable in the peripheral configtool). The DMAMUX will only start a DMA transaction when the PIT period restarts. This was sufficient for our use case.

Hope this helps other users,

Regards Rob

[DanNguyenDuy]

Hello R20220311,

This attachment file is my example ( IP layer) using DMA for both Master and Slave.

Best regards,

Dan

[R20220311]

Hi Dan,

Thanks for your example.
It uses the RTD methods to do an async transfer with DMA but what I'm missing are the following points. 

• I also used the Lpspi_Ip_AsyncTransmit method but it does not allow for periodic transfers If i'm correct.
• It can not be linked to a PIT timer instance if i'm correct.
  
  
• Furthermore this Lpspi_Ip_AsyncTransmit function uses the TDR register with the Fifo TXRX flags to push in new data, it continues with the transfer based on this flag being set.

What I would like to do is use the TDBR register to write a longer buffer once, and let the Lpspi transfer the data. In general I would like to know how the TDBR register can be used with DMA to write larger data on the LPSPI bus.

Or is the LPSPI->TDBR used for a different kind of use case?
The reference manual states it can be used to do DMA transfers on the SPI bus.

Thanks for your reply,
Hope you can give me an update,

Regards Rob van de Voort
@joohau 

[DanNguyenDuy]

Hi R20220311,

Could you send me your project (configuration files + code files)?

I will try to debug your code.

Best regards,

Dan