Hi
I was implementing the SPI functionality with the help of DMA , I found an useful example from daniel
Detailed description says :
- LPIT_ch0 triggers DMA_ch0 periodically (1ms)
- Every trigger starts a minor DMA loop (8 bytes) transfer to the LPSPI1 TX FIFO
- There are 8 minor loops per one major loop (64 bytes in 8ms)
- LPSPI1 sends two 32bit frames every 1ms
- LPSPI1 RX data are masked, they are not stored in the RX FIFO
Then I modified , it to :
- LPIT_ch0 triggers DMA_ch0 periodically (1ms)
- Every trigger starts a minor DMA loop (2 bytes) transfer to the LPSPI1 TX FIFO
- There are 3 minor loops per one major loop
LPSPI1 RX data are masked, they are not stored in the RX FIFO- DMA source array is uint16_t lpspi_tx_data[3]={0xFD00,0x0B00,0x0700};
- Each time a successful transmission of word , RDR register will be having 0xFDEF,0x0B08,0x0700 respectively
- In current configuration DMA is taking care of tx FIFO , I'm reading the received register by myself (Once interrupt is generated for Transfer word complete , I can see the value in RDR register)
- This configuration is working perfectly fine
Later I tried to add one more DMA channel to read RDR register value:
- Added LPIT_ch1 to trigger DMA_ch1 periodically(1ms)
- Every trigger starts a minor DMA loop (2 bytes) transfer to the receive array from RDR register
- There are 3 minor loops per one major loop
- So basically for every 1ms DMA will read RDR register
- From my observation , I'm guessing the issue is with delay of LPIT (I guess I'm reading RDR register at wrong time)
- Right now , I don't have any scope to verify the timing , please help to solve this issue
- Let me know what might be the issue
Let me know if some more clarification is required from my side
I have attached the project from the reference
Best Regards
KARTHIK SV
