Hard fault during hse firmware install

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Hard fault during hse firmware install

486 次查看
vikmonti7804
Contributor III

Hi,

    We flashed the hse firmware in the mcu and also We are initializing the MCU clock in our bootloader firmware. after reset the mcu I am experiencing the hard fault in MCU clock init from register level.

Then i commented the MCU clock init in bootloader firmware and then program is running without any hardfault.

Does it mean HSE is initializing the clock inside its firmware?

Or what can be reason for the hard fault, any clue?

please provide answers.

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455 次查看
Robin_Shen
NXP TechSupport
NXP TechSupport

Hi 

Please check if it is related to the reasons mentioned in the following discussion:
If I don't give s32k312 delay, the CAN stop during operation
S32K3_HSE_BUG_RTD2.0.x


Best Regards,
Robin
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436 次查看
vikmonti7804
Contributor III

Hi robin,

        You can try with the board with HSE firmware installed on it and use the example code Dio_Example_S32K312, then you will see that the firmware is going into hard fault due to the function called Mcu_InitClock(McuClockSettingConfig_0);.

If i comment this function from the main file then there is no hard fault and led start toggling so my question.

How is this LED toggling without clock init?

Does HSE firmware is initializing the clock for MCU?

Please let me know these answers.

 

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431 次查看
Robin_Shen
NXP TechSupport
NXP TechSupport

Could you share the S32DS version you are using and also the RTD version? So that I am able to verify if this is a problem related to a specific version of the tool.

Also, have you checked the two discussions mentioned in my last reply?

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425 次查看
vikmonti7804
Contributor III

I am using RTD version is 4 4 0 and SW Version 2 0 3

DS version i am using Version: 3 4

I tried 

Changes done in file structure Mcu_aClockConfigPB_VS_0 in the file Clock_Ip_VS_0_PBcfg.c.

Change the value from 1 to 0 for FIRC clock and DIO example code is starts to run with HSE firmware.

But i need to justify why this is happening?

what is the reason behind this ?

Please check attached image.

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417 次查看
Robin_Shen
NXP TechSupport
NXP TechSupport

After the HSE FW is installed, the highest 3 bits(APP_CORE_ACC) of the GPR register are set to 0, which means that the application core cannot change the FIRC divider.

36.5.13 Configuration REG_GPR (CONFIG_REG_GPR) APP_CORE_ACC.png

However, the RTD 2.0.x code does not check if it can be changed, so the system will directly enter the hard fault.

In HSE-RM, it says the FIRC divider can be modified by call the HSE service.

Robin_Shen_0-1715326895261.png

Robin_Shen_1-1715326895421.png

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412 次查看
vikmonti7804
Contributor III

So how much is the clock frequency for core from HSE?

Does HSE FW initialize the clock ? and at what frequency?

Do we need to initialize clock additionally in application?

Please clear asap.

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392 次查看
Robin_Shen
NXP TechSupport
NXP TechSupport

The proper operation of the HSE subsystem depends on the correct configuration of the clocks CORE_CLK, HSE_CLK, AIPS_SLOW_CLK, AIPS_PLAT_CLK, etc. Therefore, users need to follow the chapter 14.2.2.2 Clock Frequency Options for Devices of RM758223-HSE-B Firmware Reference Manual - V2.3(2.3).pdf, otherwise the HSE may not operate properly, or even HSE FW will be erased. Please initialize clock in your application.

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