FlexCAN Reception for any number of incoming message ID's

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FlexCAN Reception for any number of incoming message ID's

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nitinverma
Contributor III

We are working on Evaluation Board S32K144. I just want to receive the data for whatever incoming Id without Rx FIFO(Id's are unknown).
I have done with the single Id configuration for particular message buffer and its working fine.

FLEXCAN_DRV_ConfigRxMb(FSL_CAN0, 1UL, &gstr_vRx_Info_Cfg_CAN, 0x0au);

FLEXCAN_DRV_ConfigRxMb(FSL_CAN0, 2UL, &gstr_vRx_Info_Cfg_CAN, 0x0bu);

 

FLEXCAN_DRV_RxMessageBuffer(FSL_CAN0, 1UL, &gastr_vRXMsgBuffer[0]);

FLEXCAN_DRV_RxMessageBuffer(FSL_CAN0, 2UL, &gastr_vRXMsgBuffer[1]);

 

These are the APIs which I have used, as you can see MB1 is configured for ID 0x0A and MB2 is configured for ID 0x0B and we get the interrupt only for these mentioned ID's and able to receive data.Interrupt won't be generated for any other ID's.

 

Now I have hundred,thousands of unknown incoming IDs What changes do I need to make,interrupt should be generated for all incoming ID's, with the above approach its seems impossible to achieve the task.

 

Kindly let me know what needs to be done with limited number of message buffer and more number of incoming ID's.

 

Thanks,

Nitin verma

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PetrS
NXP TechSupport
NXP TechSupport

Hi,

 

You can just set a mask acceptance register(s) properly, means clear all bits. In that case the received ID is “don’t care”. If you want to receive both standard and extended frames then at least 2 MBs should be set for receive, one for standard (IDE=0) and other for extended frames (IDE=1).

 

BR, Petr

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981 Views
PetrS
NXP TechSupport
NXP TechSupport

Hi,

 

You can just set a mask acceptance register(s) properly, means clear all bits. In that case the received ID is “don’t care”. If you want to receive both standard and extended frames then at least 2 MBs should be set for receive, one for standard (IDE=0) and other for extended frames (IDE=1).

 

BR, Petr

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nitinverma
Contributor III

Hi Petr,
Thanks for the reply.
Now I have used register CAN_RXMGMASK with bit position 18 to 28 set as zero(i.e dont care) for Standard ID's.Now in this case I am getting an reception interrupt for Tx ID's as well.
Case 1: I have configured MB0 for TX and cyclic Tx ID's are sent.For these Tx ID's I am getting an reception interrupt where i have not sent any Rx ID from CANoe.
Case 2: If I transmit any Rx ID from CANoe other than TX ID, I am getting a reception interrupt for that particular Rx ID.
Kindly let me know what other changes need to be done.
Here in my case MB0 is used for TX and MB1 is used for RX, how to set the masking register only for MB1 which is for reception.

Thanks,
Nitin verma

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PetrS
NXP TechSupport
NXP TechSupport

Hi Nitin,

set the MCR[SRXDIS] bit during the Freeze mode. Once set the self reception is disabled.

BR, Petr

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nitinverma
Contributor III

Hi Petr,
Thanks for the reply now its working . I have another doubt now, what is the importance of the ID as the 4th argument in the config API 

FLEXCAN_DRV_ConfigRxMb(FSL_CAN0, 1UL, &gstr_vRx_Info_Cfg_CAN, 0x0au);

FLEXCAN_DRV_RxMessageBuffer(FSL_CAN0, 1UL, &gastr_vRXMsgBuffer[0]);

Question 1. since we are using mask register, ID parameter as an argument will be don't care, what should be the value in that config API?

 Question 2. Also, now in my case I am using XCP so i need one MB for reception ID 0x12 and another MB for remaining reception ID's(which is set to don't care), how to make use of masking register for two different MB's (i.e MB1 is having one fixed ID for XCP(0x12) and MB2 should receive all other remaining ID's except 0x12.)

Thanks,
Nitin verma

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