Disable and re-enable UART with VLPS mode of operation

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Disable and re-enable UART with VLPS mode of operation

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1,490件の閲覧回数
__invited__hari
Contributor V

Hello Team,

This is about S32K148 power down modes and LPUART.

I am able to switch between VLPS and RUN modes with UART enabled.

But my use case is to enable UART only during RUN mode and disable that communication in VLPS mode. 

I am able to disable the interrupt, but not renabled with below code sequence

PSEUDO CODE:

INT_SYS_DisableIRQ ( LPUART2_RxTx_IRQn );
POWER_SYS_SetMode ( VLPS, POWER_MANAGER_POLICY_AGREEMENT )
INT_SYS_EnableIRQ ( LPUART2_RxTx_IRQn );

Can someone suggest with any example code to do the same please?

Thanks,

Hari

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danielmartynek
NXP TechSupport
NXP TechSupport

Hello,

The INT_SYS_DisabledIRQ and INT_SYS_EnableIRQ functions disable and enable the interrupts in the NVIC registers only. The LPUART module is off in stop modes if LPUART_CTRL[DOZEEN] = 1 anyway.

The FIRC, SPLL, SOSC clock sources must be disabled before the transition to VLPS and the current SDK driver disables them. So, if you want to use LPUART once it is in RUN again, you need to ensure that the LPUART clock is enabled.

Regards,

Daniel

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1,243件の閲覧回数
__invited__hari
Contributor V

I just found a solution, but not sure that is the right way of doing it.

What I did is, I switched the clock source of LPUART to FIRC and configured that clock as disabled in 'low power' mode.

Please confirm that this is the correct solution to my use case as explained above.

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danielmartynek
NXP TechSupport
NXP TechSupport

Hello,

The INT_SYS_DisabledIRQ and INT_SYS_EnableIRQ functions disable and enable the interrupts in the NVIC registers only. The LPUART module is off in stop modes if LPUART_CTRL[DOZEEN] = 1 anyway.

The FIRC, SPLL, SOSC clock sources must be disabled before the transition to VLPS and the current SDK driver disables them. So, if you want to use LPUART once it is in RUN again, you need to ensure that the LPUART clock is enabled.

Regards,

Daniel

1,243件の閲覧回数
__invited__hari
Contributor V

Thanks Daniel for the clarification

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