adc result is not in line with expectations

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adc result is not in line with expectations

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shiyiheng
Contributor I

I use BSP34 version code, RDB3 development board,adc in2 is connected to 3.3v,adc in4 is connected to 1.8v, and adc in5 is connected to 3.3v by default on the development board.

cat in_vlotage2_raw 

3594

cat in_vlotage4_raw 

2041

cat in_vlotage5_raw 

3140

cat in_vlotage_scale

0.439453125

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Daniel-Aguirre
NXP TechSupport
NXP TechSupport

Hi,

Are you only seeing these measurements under Linux itself? Or are you also seeing them under uboot? Can you help us share all the steps done prior to reading the ADC channels?

Also, we see the following note under the BSP User Manual [Page 101, BSP34.0 User Manual for S32G3 platforms]:

" On S32G399A RDB3 on each SAR_ADC channel there is a resistor divider circuit, which increases the
S32G399A RDB3 voltage detection range (from 0-1.8V to 0-3.6V). Therefore, on S32G399A RDB3 platform, the SAR_ADC
Linux driver outputs the voltage read after the resistor divider circuit, which is half of the voltage applied."

Overall, we are not seeing any problems with ADC usage and BSP34.0.

Please, let us know.

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140 Views
Daniel-Aguirre
NXP TechSupport
NXP TechSupport

Hi,

Are you only seeing these measurements under Linux itself? Or are you also seeing them under uboot? Can you help us share all the steps done prior to reading the ADC channels?

Also, we see the following note under the BSP User Manual [Page 101, BSP34.0 User Manual for S32G3 platforms]:

" On S32G399A RDB3 on each SAR_ADC channel there is a resistor divider circuit, which increases the
S32G399A RDB3 voltage detection range (from 0-1.8V to 0-3.6V). Therefore, on S32G399A RDB3 platform, the SAR_ADC
Linux driver outputs the voltage read after the resistor divider circuit, which is half of the voltage applied."

Overall, we are not seeing any problems with ADC usage and BSP34.0.

Please, let us know.

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