S32G2 - Aurora Connector Interface

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S32G2 - Aurora Connector Interface

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gopalakrishna
Contributor I

Hi,

In one of our development project, we are using NXP S32G2 processor and interfacing with Aurora Trace connector.

On layout point, placement of Aurora Trace connector and signals routing are meeting layout guidelines of Aurora Trace connector (AN12530).

But not clear on length of differential pair. same is compare in RDB2 layout, it is ~1200mils, whereas in our PCB it is ~4500mils Max.

Here is the details about the PCB Layout:

1. No of layers : 10 layers

2. Signals (AUR_TXP2, AUR_TXN2) :  Routed in layer 3

3. Signals (AUR_TXP0, AUR_TXN0) : Routed in layer 3

4. Signals (AUR_TXP1, AUR_TXN1) : Routed in layer 1 (Top Layer)

5. Signals (AUR_TXP3, AUR_TXN3) : Routed in layer 1 (Top Layer)

6. Signals (AUR_REF_CLKP, AUR_REF_CLKN) : Routed in layer 3

Attached the images of RDB2 and our PCB layouts for reference.

Query:

1. As signals length is high, Is there any effect on functionality of Aurora interface?. 

2. Is it Okay, signals routed inner layers of layout and in multiple layers? (As per AN12530,Preferably on the top or bottom plane of the board).

3. Signal Integrity (SI) to be performed for Aurora signals?

gopalakrishna_0-1694582501044.pnggopalakrishna_1-1694582708497.png

Thank you.

Regards,

Gopala

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Daniel-Aguirre
NXP TechSupport
NXP TechSupport

Hi,

Below will be some comments on regards of your questions:

Q1. As signals length is high, Is there any effect on functionality of Aurora interface?. 

A1 >> We are not seeing any restrictions on regards of length. If you are following the overall recommendations, you should not see problems with the communication. The constraint is on regards of the signal integrity itself.

Q2. Is it Okay, signals routed inner layers of layout and in multiple layers? (As per AN12530,Preferably on the top or bottom plane of the board).

A2 >> The following is told under the AN12530:

"The differential pair should be routed with a maximum of two vias. Ideally, the differential pair should be routed without vias on a single plane of the board (preferably on the top or bottom plane of the board). "

The ideal layout should be without transitions, hence all routed either on the top or bottom plane. If required, you cannot use more than 2 vias.

Q3. Signal Integrity (SI) to be performed for Aurora signals?

A3 >> Simulations are always useful when on the design process. If you follow all the constraints, you feel comfortable with the overall design,  and you got some thumbs up from your design team, then you could skip the SI simulations, but doing them might still provide possible problems with the overall layout and show some improvements that could be made. 

If it was for me, since you are mentioning some differences and if there might be any issues, I will recommend an SI simulation for confirmation of your design. Better be safe than sorry, in my opinion.

Please, let us know.

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