S32G Clock configuration in Linux

[eburley]

When you boot linux on the S32G3 from an sdcard, how are the clocks configured?

Are there settings in the Kernel? (tf-a?  uboot?)

I'd like to disable clock control on the A cores and manage the all clocks with the M7_0 core in the bootloader.

[Daniel-Aguirre]

Hi,

Can you let us know which BSP version are you working with?

Please, let us know.

[eburley]

I have BSP 39.0

I'm looking for the section of code where the clocks are managed.  Is it in atf, uboot, the kernel, or all 3?

Currently, my bootloader configures the clocks, starts the A53, de-inits the clocks, and starts the app on M7_0. 

If I init the clocks in the app on M7_0, the tf-a output on the serial console gets corrupted, so I need to match the clock configuration on the M7_0 to what the code on the A53 expects.

I would like to configure the clocks in the bootloader and then verify the operation on the M7_0 core app to maintain a safe state. (26262)

I would like to verify that the linux kernel (and the A53 in general) cannot interfere with the clocks and take the device out of a safe state.

[Daniel-Aguirre · Accepted solution]

Hi,

Thanks for your feedback.

For what we are able to see, the clocks seem to be enabled under ATF. We are not seeing anything under uboot or Linux (at least for the overall clock_init related function). Also, we have the following information:

"They can use the XRDC module to isolate clocking peripherals(periph pll, accel pll, mc_cgm,etc) such that they are used only within a domain with one of the cores as the master."

Please, let us know.

[eburley]

What are the default clock settings that atf either sets or is expecting?

In the arm-trusted-firmware git directory, I'm looking at include/dt-bindings/clock/s32gen1-clock-freq.h, lines 33-43:

#elif defined(PLAT_s32g3)
#define S32GEN1_A53_MAX_FREQ (1400 * MHZ)
#define S32GEN1_A53_MIN_FREQ (48 * MHZ)
#define S32GEN1_ARM_PLL_VCO_MAX_FREQ (2800 * MHZ)
#define S32GEN1_ARM_PLL_PHI0_MAX_FREQ (1400 * MHZ)
#define S32GEN1_A53_FREQ (1400 * MHZ)
#define S32GEN1_ARM_PLL_VCO_FREQ (2800 * MHZ)
#define S32GEN1_ARM_PLL_PHI0_FREQ (1400 * MHZ)
#define S32GEN1_XBAR_2X_FREQ (800 * MHZ)
#define S32GEN1_PERIPH_PLL_PHI0_MIN_FREQ (100 * MHZ)
#define S32GEN1_PERIPH_PLL_PHI2_MIN_FREQ (40 * MHZ)

Is it expecting the clock to be 1.4GHz? 

The max speed for the part is 1.3GHz, which is also what the kernel reports as the rate.

If I set it to 1.3GHz in the bootloader and don't de-init the clocks, the serial output from atf is corrupted and uboot never starts.

[Daniel-Aguirre]

Hi,

Thanks for your feedback. We understand that the default values are those shown under the non-modified version of the file you are seeing.

As for the values, this might be related to tolerance, but the modification corrupting the serial console seems to be a bug. We will confirm this situation with the related team.

We apologize for any delay.

Please, let us know.

[Daniel-Aguirre]

Hi,

For what we were able to get, seems to be a bug under the BSP. The related team has been noticed about this situation.

We do apologize for the inconvenience.

Please, let us know.