Can we reduce or increase the recommended capacitors values in a custom design?

[Jerry_Huang]

can we reduce or increase the recommended capacitors values in a custom design?

for case1: 

Delete 7 2.2uf caps, add 10 1uf caps and 10 0.22uf caps.

for case2:

For pin H11, 0.1uf and 10uf required, changed to:

0.1uf, 10uf and 22uf.

[Tao_Xue · Accepted solution]

Hi Jerry,

For adding decoupling capacitance, this is acceptable from the S32G point of view, but also need to consider the PMIC requirement for total load capacitance.

For reducing the decoupling capacitance, this is not allowed because it is clearly stated in the HDG that the decoupling capacitance is "mandatory (minimum)"

For VDD, VDD_IO_DDR0, there were many discussions internally and the following consensus was reached:

1. For VDD and VDD_IO_DDR0, the PDN target impedance must meet the HDG requirements.
2. For VDD and VDD_IO_DDR0, the total capacitance must be greater than the requirements in the table " Decaps and Ferrite Bead requirement
   ". ( The total capacitance of the VDD power rail is greater than 76uF; The total capacitance of the VDD_IO_DDR0 power rail is greater than 12.6uF)
3. For VDD and VDD_IO_DDR0, any combination of capacitors can be used as long as 1 and 2 are met.
4. NXP only verifies the combinations in the table, the customer verifies the selected capacitor combination by himself.

BR,

Tao