S32K324 board hardware CRC engine and DMA configuration

[soniyajchand]

Hi,

I am trying to perform a startup CRC check on Pflash contents. I have a total of 1616KB data in Pflash and for the CRC check I am planning to use hardware CRC module of the board. To perform this, I am planning to configure a DMA channel which would transfer the contents from Pflash in blocks. Transferring 4bytes of data at a time to the Data Register of CRC Engine. Since, the maximum content the destination can hold is 32bits (Data Register). Hence the transfer size that would be configured would be 4bytes at a time. I have also read; the CRC engine places the calculated CRC results also in the Data register.
My doubts here are:
1. Will a data register update alone trigger a CRC calculation? Or should any driver API to be called for CRC calculation to begin

2. If both data and CRC calculated contents are placed in the data register, how is the CRC result not overwritten by the continuous data written by DMA to data register?

Any input would be helpful.

[soniyajchand]

Thank you, Lukas, for the information. I have gone through the sample code shared and got clarity. There are few more points.
I have a total of 1616KB of data to be transferred.
I have configured 4 bytes as the Transfer size per minor loop.
The maximum number of CITER iterations allowed is 2^15 and with this a total of only 128KB can be transferred.
So, in such a scenario, what is the ideal way to configure?
Can multiple DMA channels be used for this scenario? or
A single channel be used, with data sent as blocks, TCD be reconfigured each time after a full block of 128KB is sent and CSR.DONE =1 is received?
Which would be a better approach here for quicker transfer and CRC smooth performance

Regards,

Soniya Chandran

[lukaszadrapa · Accepted solution]

If you have spare DMA channels then linking is possible. But you need 13 channels...

Another option is to use scatter-gather feature - you will have 12 additional descriptors prepared somewhere in the memory and those will be loaded automatically one by one.

Or, if some SW overhead is not a big deal, you can use DMA interrupt and you can update the channel and start next transfer by software several times.

In my opinion, the most effective solution for this use-case is probably scatter-gather.

Regards,

Lukas

[soniyajchand]

I will try with the scatter gather option and see if it satisfies the requirement.

Thank you for the inputs, Lukas.

Regards,

Soniya Chandran

[lukaszadrapa]

Hi @soniyajchand 

yes, it's that simple. The write itself triggers the calculation. No other actions are needed. You can take a look at this thread:

https://community.nxp.com/t5/S32K/S32K148-Is-it-possible-to-use-DMA-for-CRC-Calculation/m-p/1196173

It's still the same like on mentioned S32K1 and MPC5 devices. You can take a look at the mentioned example.

And it corresponds to the functional description in the reference manual:

Regards,

Lukas