Xgate Software Interrupt Peroid

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Xgate Software Interrupt Peroid

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rayhall
Contributor V

I am running the S12XE at 48 MHz. I read that Xgate executes code at twice the main processor core. So based on this the software interrupt event in the code below is every 1.04 uSec. Correct ?

Ray.

// interrupt handler
interrupt void SoftwareTrigger0_Handler(MyDataType* __restrict pData) {
 
  // put your own code here
  pData->counter++;
  if (pData->counter > 100)  {
    pData->counter= 0;
    shared_counter++;
  }
}

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lama
NXP TechSupport
NXP TechSupport

Hi,

the main fact and difference is that the CPU uses CISC set of instructions and XGATE is a RISC core. The code is written in C so nothing is clear and easily to be calculated.

The easiest way to check number of cycles which given routine takes is to open project in simulator target and step it either via C or ASM code. I suppose you use CodeWarrior IDE.

As you can see in the picture both cores are able to be simulated and stepped.

Another way to be sure about exact number of cycles is to have everything in your hands and write the code in assembler together with cycles calculation with the data taken from CPU and XGATE core manuals. A number of cycles or time in us can be seen in the bottom of the simulator window (for example here, 120 CPU bus cycles has gone and 2MHz BUSCLK is used)

pastedImage_1.png

Best regards,

Ladislav

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