Hi,
You wrote you set LPDTIE but..
LPDTIE, LIN transmitter TxD-dominant timeout Interrupt Enable
0 Interrupt request is disabled. / 1 Interrupt is requested if LPDTIF bit is set.
LPOCIE - LIN transmitter Overcurrent Interrupt Enable
0 Interrupt request is disabled. / 1 Interrupt is requested if LPOCIF bit is set.
Also check you have enabled global interrupt enable….. from the CPU manual
7.3.5 I-bit-Maskable Interrupt Requests
Maskable interrupt sources include on-chip peripheral systems and external interrupt service requests. Interrupts from these sources are recognized when the global interrupt mask bit (I) in the CCR is cleared. The default state of the I-bit out of reset is 1, but it can be written at any time if the CPU is not in user state. The interrupt module manages maskable interrupt priorities. Typically, an on-chip interrupt source is subject to masking by associated bits in control registers in addition to global masking by the I-bit in the CCR. Sources generally must be enabled by writing one or more bits in associated control registers. There may be other interrupt-related control bits and flags, and there may be specific register read-write sequences associated with interrupt service. Refer to individual on-chip peripheral descriptions for details.
BTW, we do not suggest to use PE as development platform because the evolution was closed long time ago and no bug will be neither investigated nor corrected. Of course, it is suitable to be used as teaching tool, but from my experience, it is better to have everything under own control.
Best regards,
Ladislav