Dears,
Recently we decided to redesign the PCB of one of our products that uses 9S12XEQ512 MCU.
On the datasheet, the power input to the voltage regulator is pin 31 VDDR.
Based on this, on the old version of the PCB, the central power connection is on PIN 31 like on picture old.jpg. The Ground polygon pour below the processor connects to the ground plane at one location on VSS2 pin through single via. The ground plane is directly below the top layer. But this is not according to the recommendations of page 1263.
On refererence manual page 1263 Appendix C PCB Layout Guidelines there are the following suggestions
Central point of the ground star should be the VSS3 pin. (pin 32)
Central power input should be fed in at the VDDA/VSSA pins. (pins 59 & 62)
Is the existing PCB routing for power and Ground considered satisfactory and robust for ESD purposes?
Why is the recommendation for central power connection at VDDA VSSA and not to the Voltage Regulator pin VDDR? Is it to reduce the noise on the analog domain only, or it affects EMC/ESD performance as well?
Finally if the central power connection return is VSSA, then where should the Ground plane be connected? At VSS3 or VSSA?
Please have a look at the new proposed routing at new.jpg. In the second image, 3V is not routed below the IC, and power is routed from VSSA and VDDA pin and not VDDR pin. The supply to VDDR has to pass through two vias to reach there. Ground connection to Ground plane is near VSS3.Bottom layer parts are connted to 3V before the main ground connection. Should the main ground also be directly connected to pin 62 ( I added resistor footprint for this), or is it ok to use the ground plane only?
Are there any advantages to this approach? Will it have optimal ESD performance? Or should we keep the old routing which we already know has no problems with ESD discharges?
Best Regards,
