Regarding dead time insertion in complimentary mode for S12ZVM

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Regarding dead time insertion in complimentary mode for S12ZVM

Contributor V

Dear Team,

Thanks for your continuous support.

I am using edge aligned complimentary mode in SW. Below are my queries,

1. When PWM is applied to Phase A then at first LS will be ON or OFF? What will be the behaviour of HS and LS?

2. Second query is explained though below image, considering as LS will be off first when PWM is applied to phase A.


As per the above image. Our understanding is that "after LS off, HS will be ON after delta t deadtime and after HS off, LS will be on after delta t deadtime. Deadtime will be added on both ends."

Please confirm the understanding is correct or not.

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NXP Employee
NXP Employee

Hello Pratibhasurabhi,

Ad 1)

When you use the standard half-bridge driver for MOSFETs power stage, it uses the boost capacitor to supply high side driver. So the first must be activated low side MOSFET.

The association of complementary channels is in Table 15-18. This means the main channels are Ch_0, Ch_2 and Ch_4.

All depends on the used driver (let use the a standard type – log1 on LS_IN activates the low side MOSFET) then the PWM period must start with PWM_L = 1 and PWM_H = 0 (MCU outputs). This means in complementary mode the PWM output is negated –> PWM_H starts with log0 and channel value = 1-DUTY.

Then for small DUTY the most of period is PWM_H = 0 and PWM_L = 1. The PWM period starts with PWM_H = 0 and PWM_L = 1 – this fits to the standard half-bridge MOSFET driver.

Ad 2)

Please see in Figure 15-41 the detail signal paths. The dead time is inserted always on starting positive output (to delay switch-on of MOSFET) no matter if high-side or low-side – Figure 15-51. Please refer to Figure 1-10 also.

I thing it could help you to solve your task.

Best Regards,



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