PIT using Xgate on s12xdp512

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PIT using Xgate on s12xdp512

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Contributor I
hi,
 
Using xgate i made two seperate interrupt time out routine of PIT timer (say channel 0 , and 1), but xgate can only generate one time out perid for channel 0 of PIT, he not able to genetate interrupt for channel 1 why? i cant get it.
                           please any body tell how to add more than one interrupts in xgate file.
i am using s12xdp512 and codewarrier 4.5 version
 
 
please hepl mi in this reguards
 
vinay
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Contributor I
hi again,
 
I enable the channels 0 & 1 interrupt simultaneously. but channel 0 only get overflow interrupt in xgate file, as i am trying these two overflow interrupt in normal main file then it works fine ie independatly but same not working on xgate.
 
 
please help me in this reguards
 
vinay
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Specialist I
Are you using PIT module from both cores, S12X and XGATE? If so, then did you prevent simultaneous accesses from S12X and XGATE to flags and other PIT registers with semaphores?
 
Also I hope you aren't using something like this flg_register |= mask to clear PIT flags, are you?
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Contributor I
 
Ya, I am using PIT module in both cores, but i dont understand how to prevent simultaneous accesses from S12X and XGATE to flags and other PIT registers with semaphores? please explain me if any ex. code available.
             and i dont  using something like this flg_register |= mask to clear PIT flags,
one more thing i want to add my xgate not working when i write more than two different interrupt also> i cant understand where am i rong???
 
vinay 
 
 
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Specialist I
You said xgate not working when you write more interrupts. It sounds like you forgot to clear interrupt flag in some XGATE interrupt handler/handlers. It also could be a usage of bitfields to clear interrupt flags. It could be, like I said previously, something like 
 
     flags_register |= flag_bitmask;  // wrong
 
or
 
     flags_register = flags_register | flag_bitmask;  // wrong
 
It also could be a bad interrupt routing, a bug in XGATE vector table etc etc. It would be much easier to help if you would show us your code that doesn't work.
 
Regarding simultaneous accesses to shared resources from CPU12X and XGATE. Shared resource could be for example PIT flags register PITTF, PIT interrupt enable register PITINTE or any other thing, both cores can access simultaneously. Read accesses to shared resources shouldn't be problematic. But write accesses can be dangerous. For example you want to clear from S12X port PTT pin 5 and at the same time XGATE is going to toggle PTT6. Will XGATE a) read PTT register before S12X will read PTT, b) after S12X read but dindn't yet write PTT back, c) maybe after S12X cleared PTT5? Cases a and c are quite safe, but b is undefined and dangerous. You should use XGATE semaphores to prevent case b.
 
I'm attaching my example, where S12X uses PIT3 interrupt to toggle PTT5. And XGATE uses PIT2 to toggle PTT6. Try to remove somephore locking/unlocking code and see how it affects a quality of meander on PTT5 and PTT6.
 
BTW i'm sort of fixing myself, you don't need semaphores to clear PIT flags from both cores. It's because when you want to clear PIT0, you don't have to preserve the state of all other flags PIT1-PIT4 by reading them and saving them back, you just have to write one to PIT0 and zeros to PIT1-PIT4.
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Contributor V
Yo,

There is only one vector for PIT. As you got Overflow on Channel 0, the redirection of Interrupt is fine.
But have you enabled interrupts for other channels ?

See PITINTE_PINTEx configuration bits.

Cheers,
Alban.
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