MC9S12XEP100 Problem with Xgate and PIT 3 not always interrupting

[mcjag]

Hi

I am having trouble with using PIT timer 3 on the xgate of a MC9S12XEP100.  The ISR for PIT3 is serviced on the xgate, and is used a "tick" to run the code on the xgate. At the end of the ISR, the xgate disables PIT 3, changes the interrupt period to a value between 80us and 1.5ms, and then re-enables PIT 3, finally it clears the intterupt. The code used to do this is below.

PITCE_3 is #defined as 0x8 and TIMER_TICKS_US works out at 1.

    while (!_ssem(XG_SEM_PIT))    {    }    PITCE = (PITCE & (~PITCE_3));  /* Disable the PITCE_3 Timer */    PITLD3 = ((CurrentTickRate * TIMER_TICKS_US ) - 1U);   /* Sets up PIT3 for the xGate timing interrupt period */    PITCE = (PITCE | PITCE_3); /* Reset and Enable the PITCE_3 Timer */    _csem(XG_SEM_PIT);

The S12x uses some of the other timers, but PIT 3 is exclusively for one ISR on the xgate. All access to the PITCE register is protected by the same semaphore on both the S12x and the Xgate.

The problem is as follows:

This works fine for a while (between 30 mins, and several hours), but after a seemingly random ammount of time, the PITCE register no longer enables PIT3,  Thus the xgate stops ticking, and the things the xgate do, stops. All the other S12x timers continue to work ok.  I use a variable to track if the xgates timing ISR has run since the start of the last S12x frame (which is 25ms long)  . When I detect that it hasn't executed I dump out all the values of th PIT registers

 PITCE:0x17 PITTF:0x4 PITCNT3:0x013 PITLD3:0x13PITINTE:0x9 PITMTLD0:0x27 PITMUX:0x4

using a GPIO pin driven by the xgate, I can tell that the xgate gets to the very end of the ISR (past the point where it sets the PITCE register)

It says in the datasheet that if the PCE bit in PITCE is cleared, the pit channel is disabled and the corresponding flag bit in the PITTF register is cleared, so I am using this feature to clear the interrupt and restart the timer. Is this a suitable method of implementing a variable rate timing interrupt for the xgate? Does anyone have any suggestions as to what could cause the PIT3 to stop working like this.

Cheers in advance

[kef]

Are you sure that all write accesses from S12X to PITCE and PITCE_PCEx "bits" are protected with semaphore?

[mcjag]

Yes all four calls to the PITCE register are protected by the same semaphore ( one on the xgate, three on the S12x), apart from the very first one, which sets up the system timers, however this is only called once on startup, and finishes well  before the xgate is started up and initalised. Thus it needs no protection, I have verified that this is only called once, and that all other PITCE access (both read and write) is protected by the same semaphore.

[kef]

Are you sure your S12X code to lock semaphore is OK?