External crystal fails and internal RC clock take places？

[thulzh]

We have adopted S12ZVC as the MCU in a recent controller project.

When ESD test was conducted on the controller, the fixed cycle of the 'main' function seems to slow down, which is toggled by the RTI(real time interrupt) module. External crystal (8MHz) was selected as the source for the RTI.

The visible phenomenon was  that CAN took several times longer period to send message with uninterrupted rolling counter.

I wonder if there is some auto-shift mechanism inside the S12ZVC core that the RTI's clock shift to IRCCLK when external crystal fails without reset the MCU. If there is, how it is indicated?

[lama]

Hi,

I suppose you use PEE mode.

8.4.6.2 PLL Engaged External Mode (PEE)

All other modes and lost of osc clock are also described in the RM.

......
Loosing PLL lock status (LOCK=0) means loosing the oscillator status information as well (UPOSC=0).
The impact of loosing the oscillator status (UPOSC=0) in PEE mode is as follows:
• The PLLCLK is derived from the VCO clock (with its actual frequency) divided by four until the
PLL locks again.
Application software needs to be prepared to deal with the impact of loosing the oscillator status at any
time.

Best regards,

Ladislav