Data sharing between S12x and Xgate

[rahulkrishna]

1.I am sharing some data (RAM) between s12x and xgate i know there should be data alignment between S12x

and Xgate. I am not sure whether my project follows data alignment. How to know this?

2.Should the shared data be always located in non banked RAM memory or it can be in Banked memory?

I have shared the data in banked memory. Any extra care need to be taken in case of sharing data in paged memory.

3.If the alignment is not proper between xgate and s12x, what will be the behaviour of the code.  Is the data retrieved will always be wrong or sometimes we get the expected value and sometimes unexpected value.

4.Can I copy the data from one paged memory to another paged memory? Am I correct that data can be copied

from any paged memory to the non paged memory.

[rahulkrishna]

Yes, you are absolutely correct. The structure is aligned. I am sorry I am not clear when I say linker file, I am actually referring to the map file. In the map file I can see the address of the structure variable not the members. It is ok now i got some idea if in doubt i will see the debugger memory. Many thanks for clarifying the doubts.

[rahulkrishna]

Thank you very much for the detailed explanations. First thing is

1. I have observed the linker file of the structure members, it does not seem to give the addresses of the members inside the structure. Why is it so when it is so important that objects should be placed on even addresses. Any method to enable it?

2. I have huge array of structures shared between the S12X and Xgate some of which are integer and long. I never used #pragma align on, then why my code is not failing? Any specific reason for that?

3. Final question about data sharing in banked memory.

S12x

#pragma DATA_SEG __GPAGE_SEG     PAGED_RAM

volatile unsigned char data1[12];

#pragma DATA_DEFAULT

In Xgate file

#prgma DATA_SEG __GPAGE_SEG PAGED_RAM

extern volatile unsigned char data1[12];

#pragma DATA_DEFAULT

Am I correct that xgate compiler will omit the __GPAGE_SEG as I understood from your previous explanation?

Please advise.

[kef2 · Accepted solution]

• 1. I have observed the linker file of the structure members, it does not seem to give the addresses of the members inside the structure. Why is it so when it is so important that objects should be placed on even addresses. Any method to enable it?

What is "the linker file of the structure members"?

• 2. I have huge array of structures shared between the S12X and Xgate some of which are integer and long. I never used #pragma align on, then why my code is not failing? Any specific reason for that?

Perhaps your struct is organized so that align on / off don't matter. For example

struct {

    char c;   // offset 0

     int i;      // offset 1 with align off and offset 2 with align on

...

You may avoid using align on making all members word aligned like this

struct {

    char c;   // offset 0

    char dummy;  // fix alignment issue

     int i;      // offset 2 with align off and offset 2 with align on

...

• Am I correct that xgate compiler will omit the __GPAGE_SEG as I understood from your previous explanation?

Yes. XGATE address space is 64 kB only, no paging is available on XGATE, __GPAGE_SEG is ignored.

Edward

[lama]

It is not clear whether you use S12XE or S12XD family device, however the approach is the same. I have attached an example code for S12XD where you can see how I share large array and port B between XGATE and CPU.

(XDP512 - SHARED 3x2000Bytes - CW45)

The difference between XD and XE is that in the case of XD one mask set has an errata so it is necessary to write:

asm SSEM #0 // try to lock semaphore 0     // once more due to internal silicon bug

as can be seen in the xgate.cxgate file. In the case of XE mcu it is not necessary

I believe the example will help you to understand. Just check files xgate.cxgate, xgate.h and main.c.

Moreover, you should be sure the placement of variables is correct. In order to explain I have attached memory maps of S12XEP100 and S12XD512. In the column M you can see addresses where the XGATE sees the memory. The CPU sees the same addresses differently as can be seen in columns D, F and I+K in dependence of the addressing mode. (Global, direct, rpage, ppage)

I have attached a few more examples, however, there is no semaphore used if it is not necessary from the principle of work. (no possibility to access shared variable simultaneously from both cores.

So back to your question:

1) Please compare your project with attached

2) In the attached excell sheets you can find all possible addresses where XGATE is able to address data.

3) Wrong, especially I have run into troubles when I shared structures and I used size of byte variables. A standard mistake. I suppose to use always integers as the least of size variable type to be always aligned. Alignment must always be to even address.

4) Yes, it is not any problem. If we talk about RAM you can use global addressing mode and then you do not have to think about pages. See attached example XEP100-RAM-RAMaddressing-CW45.zip

Best regards,

Ladislav

[rahulkrishna]

There is something i am missing in my understanding, I have created one more project without far before the variable, but the data is properly updated in the variable. What is the difference between your project and my project, I have attached the project for your reference.

[kef2]

Rahul,

Code in your Daubt*.zip is wrong. Placing data in paged RAM, you have to tell CPU12X compiler how does it need to care about page switching. It is not enough to use

#pragma DATA_SEG PAGED_RAM

^^ this line only contains information for linker that you want it to place data under this pragma in PAGED_RAM. And compiler (CPU12X) is still unaware that it needs to switch RPAGE or use global addressing to access your data. To make CPU12X compiler aware, you need to insert __GPAGE_SEG or __RPAGE_SEG like this

#pragma DATA_SEG __GPAGE_SEG PAGED_RAM

far keyword is kind of replacing __?PAGE_SEG in pragma, but IMO it's much worse than __?PAGE_SEG.

Since __?PAGE_SEG tells CPU12X compiler how data should be accessed, you need to use the same pragma in header files when sharing data among CPU12X source files. XGATE uses its own addressing mode and XGATE compiler should ignore __?PAGE_SEG pragmas.

• 1.I am sharing some data (RAM) between s12x and xgate i know there should be data alignment between S12x and Xgate. I am not sure whether my project follows data alignment. How to know this?

Shared data segment in your PRM file should haver ALIGN 2 or ALIGN 2[1:1] like this:

      RAM           = READ_WRITE  DATA_NEAR            0x2000 TO   0x3FFF ALIGN 2[1:1]; /* word align for XGATE accesses */

This should make linker placing object with sizeof(object)>=2 at even addresses.

Also sharing struct's between XGATE and CPU12X, you should use

#pragma align  on

in CPU12X to ask compiler to word align struct members. The same like with #pragma DATA_SEG pragmas, #pragma align on for shared data should be visible in all CPU12X source files, which are making access to "#pragma align on"'ed structs.

• 2.Should the shared data be always located in non banked RAM memory or it can be in Banked memory?I have shared the data in banked memory. Any extra care need to be taken in case of sharing data in paged memory.

Yes, shared data can be banked. There should be no problems with this, unless you try to share pointers. Data pointers are not compatible between XGATE and CPU12X. Some tricks are possible, but you should not share any pointers between cores. Use indexes instead.

• 3.If the alignment is not proper between xgate and s12x, what will be the behaviour of the code.  Is the data retrieved will always be wrong or sometimes we get the expected value and sometimes unexpected value.

Sometimes good, sometimes not. XGATE can't read word from odd address, it must be even. If you are not sure about alignment, make XGATE reading upper and lower bytes of word and then glue them into word. Just use ALIGN in PRM and #pragma align on.

• 4.Can I copy the data from one paged memory to another paged memory? Am I correct that data can be copied from any paged memory to the non paged memory.

No problems with correct -PSegXXX compiler switch.

Hope this helps

Edward