CW12 V3.1 - New Installation, Build Errors for Supplied Beans

[almcneil]

I am new to my position. This company has an older product that was developed under CodeWarrior for MC9S12E128.I installed CW12 v3.1 and when I went to build the project taken from source control, I got 4 build errors all to do with supplied beans. I have attached a screenshot of the build report. Since it's a new installation, there might be some configuration I need to make in order for the beans to compile. If someone can point me in the right direction I would appreciate it!

Andy McNeil | Systems Engineer

Spotwave Wireless Inc.

Kavveri Telecom Products Limited

P.O. Box 550

500 Van Buren Street

Kemptville, ON K0G 1J0

CANADA

T 613.591.1662 ext. 3336

F 613.258.7418

E andy.mcneil@kaveritelecoms.com

[RadekS]

Did you install Processor Expert updates?

http://www.freescale.com/webapp/sps/site/overview.jsp?code=CW_UPDATES_HCS12_31

[almcneil]

Thank you Radek, your answer was what I was looking for. It reduced my build errors from 4 down to 2. it's really one error now as both errors are to do with the same bean. Since the errors were to do with beans, it meant I was either missing something or not configuring Processor Expert correctly.

I am keeping this thread open until I solve the remaining bean error. Latest screenshot of build report below.

[almcneil]

I checked with the Bean Inspector and it reports that the peripheral (I/O pin) is already reserved by another device (ADDR-BUS) Screenshot below:

[RadekS]

In all modes except Normal Single Chip Mode, the PE4 pin is initially configured as the output connection for the internal bus clock (ECLK).

PE4 - Bus timing reference clock, can operate as a free-running clock at the system clock rate or to produce one low-high clock per visible access in expanded modes, with the high period stretched for slow accesses (ECLK is used as a timing reference and to demultiplex the address and data).

The ECLK frequency is equal to 1/2 the crystal frequency out of reset.

The ECLK output function depends upon the settings of the NECLK bit in the PEAR register, the IVIS bit in the MODE register and the ESTR bit in the EBICTL register.

So, everything depends on your hardware/software settings.

In Normal Single Chip Mode, PE4 works as GPIO until you clear NECLK bit in the PEAR register.

In Special Single Chip Mode, PE4 works as bus clock output. This is very good toll for debugging purposes.

In expanded modes, PE4 is used as a timing reference for external memory.

Please look at your hardware configuration (if ECLK signal is necessary) and PEAR_NECLK bit.