No. Taking a TLB error exception indicates you have a TLB miss. When you've taken a TLB miss (or executed tlbsx or tlbre) NV will contain a suggestion for which ESEL to use. Otherwise (including when taking an ISI/DSI exception, which is what you'd get with the TLB entry you showed), NV is undefined.
Did I get an ISI/DSI exception because all the permission bits are clear?
“The TLB entry’s permission bits
(TLB[US,SX,UW,SW,UR,SR]) determine whether the operation should succeed. If permission is denied,
execution of the instruction is suppressed and an instruction or data storage interrupt occurs.”
Hi Scott,
I’m working with a P2041RDB. I’m using uboot as a bootloader. Uboot sets up core 0 and holds other cores in spin loop.
Now I want to set up MMU for core 1 before I release it.
Here’s what I do to set up a mapping that maps addr 1:1 for 64M
// MAS0 = 0x10010000 (TLB1 is selected, IPROT = 1 and 1st entry)
lis r5,0x1003
ori r5,r5,0x0000
mtspr 624,r5
//MAS1 = 0xC0000800 (TSIZE = 64MB)
lis r5,0xC000
ori r5,r5,0x1800
mtspr 625,r5
// MAS2 = 0x00000210 (effective page number = 0 and effective address range = 0,
// share enabled is set and the page is set up as write-thru).
lis r5,0x0000
ori r5,r5,0x0210
mtspr 626,r5
// MAS3 = 0x00000015 (SX=1, SW=1, SR=1)
lis r5,0x0000
ori r5,r5,0x0015
mtspr 627,r5
tlbwe
msync
isync
Does that look correct? The code that I have that following this setup doesn’t work properly. So I just want to check and see if my setup was done correctly.
Thanks!
You can't set up the MMU on core 1 before you release it. You can only set up the MMU on cores you're already running on. The U-boot spin table code will create a mapping for core 1 when it is released. See the documentation of SIMA in ePAPR.
I think I got a DSI based on these values:
PC: 0x000001C0
SRR0: 0x00006090
SRR1: 0x00000000
DEAR: 0x04000000
ESR: 0x00800000
I think the instruction that caused the DSI is this:
stw r3, 0(r11)
I saw this in the EREF:
Software can determine if the exception
occurred during a page table translation by examining ESR[PT] (or GESR[PT] <E.HV>).
I can’t tell what the ESR[PT] is telling me.
Thanks!
ESR[PT] indicates the fault was from a bad entry in a hardware page table (i.e. something pointed to by a TLB1 entry with the indirect bit set). That bit is not set, so I'm not sure why you're asking about it. The only bit set in ESR above is ESR[ST], which indicates that the access was a store rather than a load.